一种新的1024点基-2 FFT旋转因子产生电路的结构

设计了一个新的无存储器的基-2 1024点FFT旋转因子产生电路.这个旋转因子产生电路用若干逻辑模块来产生数据,然后用这些数据合成所需要的旋转因子.用Synopsys Power Compiler进行功耗分析表明,用TSMC 0.25μm CMOS工艺综合出来的电路在50MHz时的功耗为2mW.这种旋转因子产生电路非常适合用于低功耗的设计中,尤其是移动通信和其他手持设备中.     

一种基于绝热电路的集成电路低功耗设计

能量通过电路损失后就会产生功耗,如能重新利用这种能量,就可以降低大部分功耗,这种技术称为能量恢复技术,其中绝热电路是一种常用的能量恢复技术,经常被用在大规模集成电路设计中,本文详细分析绝热电路的设计,以及在集成电路设计中的应用.     

可变长数据全并行FFT地址生成方法

本文通过对混合基4/2 FFT算法的分析,在优化采样数据、旋转因子存储及读取方法的基础上,提出了将N=2m点,m为奇、偶两种情况的地址产生统一于同一函数的算法,并设计了简单的插入值产生及快速插入位置控制电路,从而用一个计数器、同一套地址产生硬件,通过简单的开关模式控制,可实现任意长度FFT变换的地址产生单元,该地址产生单元在一个时钟周期内产生读取所需旋转因子及并行访存4个操作数的地址.本文设计的FFT处理器每周期完成一个基4或2个基2蝶式运算,在吞吐率高、资源少的基础上实现了处理长度可编程的灵活性,同时避免了旋转因子重复读取,降低功耗.     

具有反馈结构的PAL-2NF电路

在分析PAL-2N电路缺陷产生原因的基础上,提出了一种低功耗,具有反馈结构的PAL-2NF电路,它采用逐级相位落后90°的四相正弦功率时钟.讨论了PAL-2NF电路的设计方法,并在不同时钟频率下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟,电路能完成正确的逻辑功能.五级级联的PAL-2NF反相器/缓冲器电路在功率时钟频率10MHz时都比相应的PAL-2N电路节省93%以上的功耗,在400MHz时功耗节省也可达40%.由于几乎完全消除了输出端的悬空现象和逻辑0的"第三态"现象,PAL-2NF电路可以工作于更高的时钟频率和更低的输出波形畸变.     

能量回收电路的功耗优化方法

能量回收电路的非绝热损失正比于CLΔV2,文中提出了两种方法降低CL和ΔV因子.HEERL(high efficient energy recovery logic)电路利用自举效应减小了回收节点的残留电压ΔV,IERL(improved energy recovery logic)电路增加了回收的通路,在控制回收通路的小电容节点产生了CAΔV2的非绝热损失,从而使大电容输出节点电荷被充分回收,降低了电路的整体功耗.降低非绝热损失两个因子CL和ΔV的能量回收电路与其它能量回收电路相比,电路面积增加很小(2个NMOS管),而功耗可降低50%以上.     

能量回收电路的功耗优化方法

能量回收电路的非绝热损失正比于CLΔV2,文中提出了两种方法降低CL和ΔV因子.HEERL(high efficient energy recovery logic)电路利用自举效应减小了回收节点的残留电压ΔV,IERL(improved energy recovery logic)电路增加了回收的通路,在控制回收通路的小电容节点产生了CAΔV2的非绝热损失,从而使大电容输出节点电荷被充分回收,降低了电路的整体功耗.降低非绝热损失两个因子CL和ΔV的能量回收电路与其它能量回收电路相比,电路面积增加很小(2个NMOS管),而功耗可降低50%以上.     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路——complementary pass- transistor adiabatic logic (CPAL ) .电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MO-SIS的0 .2 5μm CMOS工艺,在5 0～2 0 0 MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2 N - 2 N2 P电路的5 0 %和35 % .     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

具有反馈结构的PAL-2NF电路

在分析PAL - 2 N电路缺陷产生原因的基础上,提出了一种低功耗,具有反馈结构的PAL - 2 NF电路,它采用逐级相位落后90°的四相正弦功率时钟.讨论了PAL - 2 NF电路的设计方法,并在不同时钟频率下用1 .2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟,电路能完成正确的逻辑功能.五级级联的PAL - 2 NF反相器/缓冲器电路在功率时钟频率1 0 MHz时都比相应的PAL - 2 N电路节省93%以上的功耗,在4 0 0 MHz时功耗节省也可达4 0 % .由于几乎完全消除了输出端的悬空现象和逻辑0的“第三态”现象,PAL - 2 NF电路可以工作于更高的时钟频率和更低的输出波形畸变     

一种OTP存储器高速读出机制的设计

本文设计了一种用于OTP存储器的高速读出机制.该读出机制由内部电路产生读控制时序,采用地址变化探测电路、脉冲宽度调整及控制信号产生电路、采样与锁存电路来实现读取操作.其具有电路结构简单,读出速度快,读出准确,抗噪声、抗干扰能力强,功耗低的特点.仿真结果表明整个读取周期仅为24ns,数据口的读出信号稳定准确,不会产生读取误操作.     

Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing

This paper presents an area-efficient algorithm for the pipelined processing of fast Fourier transform (FFT). The proposed algorithm is to decompose a discrete Fourier transform (DFT) into two balanced sub-DFTs in order to minimize the total number of twiddle factors to be stored into tables. The radix in the proposed decomposition is adaptively changed according to the remaining transform length to make the transform lengths of sub-DFTs resulting from the decomposition as close as possible. An 8192-point pipelined FFT processor designed for digital video broadcasting-terrestrial (DVB-T) systems saves 33% of general multipliers and 23% of the total size of twiddle factor tables compared to a conventional pipelined FFT processor based on the radix-2² algorithm. In addition to the decomposition, several implementation techniques are proposed to reduce area, such as a simple index generator of twiddle factor and add/subtract units combined with the two's complement operation     

Applications of momentary Fourier transform in frequency shift keying signal demodulation

Power line communication is attracting increasing attention for its characteristics of easy availability and low cost. Frequency shift keying with the virtue of antijamming capability is suitable for the low signal‐to‐noise ratio power line environment. The principle of the frequency shift keying communication system based on momentary Fourier transform (MFT) algorithm is provided first in this paper. Theoretically, the twiddle factor in the MFT algorithm is a decimal with infinite length. However, when it is applied on digital signal processor (DSP), the registers with finite length in DSP lead to the inaccuracy of the twiddle factor. Thus, the MFT algorithm with recursive form will cause accumulative error as a result. We analyze the impact of the inaccurate twiddle factor on the MFT algorithm from a novel point of view, by which the MFT algorithm is considered as a linear time invariant system. We prove that the accumulative error would not disperse when the modulus of the twiddle factor is smaller than 1. Simulation results show that the truncation approach is more effective than both carrying and rounding methods in a practical system. In addition, the number of significant digits of truncated twiddle factor must be chosen larger than 4 to overcome the problem of accumulative error.Copyright © 2012 John Wiley & Sons, Ltd.     

Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic. In addition, the dynamic power consumption can be reduced by as much as 15% by reducing memory accesses.     

时间抽取情况下的旋转因子合并FFT算法和TMFFT的软件实现

马滕斯(Martens)提出了一种效率高(可与WFTA法和PFA法相比拟)、结构简单(与FFT法相似)的DFT计算方法RGFA。作者已经证明,在基2的情况下,RCFA与旋转因子合并的频率抽取FFT算法是完全等价的。本文给出了旋转因子合并的时间抽取FFT算法,从而使得在任何条件下,目前使用的FFT算法都可以用外部特性完全相同、内部结构基本相同的高效算法旋转因子合并FFT算法来代替。本文还给出了实现旋转因子合并FFT算法的软件。     

FFT/DFT旋转因子生成算法误差分析及修正

旋转因子生成是FFT/DFT算法中的重要步骤,直接影响系统实现时的计算速度和资源开销。一种改进的算法给出了一个原理简单、计算速度快、占用存储资源少的旋转因子生成方案。然而系统实现时,乘加单元定点操作会引入截位或舍入误差,且该误差会随着乘加次数的增加而逐级扩散,导致旋转因子精度值下降,无法满足系统性能要求。基于FFT/DFT矩阵分解实现方式,本文给出了旋转因子生成的具体硬件实现结构,以及详细的误差分析。同时采用重定标的误差修订方案以减小误差,并推导出了重定标次数与系统给定条件之间的关系式,便于设计者进行灵活的设计。文章同时引入流水技术提高了系统速率。性能分析表明,相对于以往的算法,本文提出的算法占用的存储资源大大减少;且相对于不进行重定标方案,7次重定标能保证旋转因子精度提高约16个dB。      

TWIDDLE FACTOR MERGED TIME-DECIMAL FFT ALGORITHM AND THE SOFTWARE IMPLEMENTATION FOR TWIDDLE FACTOR MERGED FFT ALGORITHM

Martens proposed a highly efficient and simply formed DFT algorithm——RCFA,whose efficien-cy is comparable with that of WFTA or that of PFA,and whose structure is similar to that of FFT.Theauthors have proved that,in the case of radix 2,the RCFA is exactly equivalent to the twiddle factor mergedfrequency-decimal FFT algorithm.The twiddle factor merged time-decimal FFT algorithm is providedin this paper.Thus,in any case,the FFT algorithm used currently can be replaced by the more efficientalgorithm——the twiddle factor merged FFT algorithm,with exactly the same external property and thesimilar internal structure.Also in this paper,the software for implementing the twiddle factor merged FFTalgorithm(TMFFT)is provided.     

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2^k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm². The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.     

FPGA implementation of high-performance,resource-efficient Radix-16 CORDIC rotator based FFT algorithm

The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (CORDIC) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, CORDIC needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 CORDIC algorithm takes n/4 iteration as compared to n iteration of the radix-2 CORDIC algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex−7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.     

超长点数FFT处理器的旋转因子生成方法

对于大点数FFT处理器,提出了一种新的旋转因子生成方法。首先对三角函数曲线分段进行折线近似,将线段端点及斜率存入存储器,然后通过查表以及插值计算的方法来生成旋转因子。在保证FFT计算精度的前提下,极大地降低了对旋转因子存储器容量的需求,对大点数FFT处理器的单片ASIC实现具有重要意义。     

一种实序列FFT算法改进及其在DSP上的实现

FFT是数字信号处理最重要的算法之一,论文分析了常规的2N点按时间抽选的实序列FFT运算的基本原理,介绍了一种改进的算法,算法将奇数序列和偶数序列部分开计算,并提取旋转因子的公因子,大大减少了计算过程中的加法和乘法的个数和旋转因子的引用次数,并在实际的DSP平台上进行了实现,实验数据表明,该算法在运算效率和复杂度上都较传统FFT算法有较大的改进。