共查询到18条相似文献,搜索用时 171 毫秒
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针对沟道下方开硅窗口的图形化SOI(PSOI)横向双扩散MOSFET(LDMOSFET)进行了结构优化分析,发现存在优化的漂移区长度和掺杂浓度以及顶层硅厚度使PSOI LDMOSFET具有最大的击穿电压和较低的开态电阻.PSOI结构的RESURF条件为Nd·tsi=1.8~3×101 2cm-2.对结构优化的PSOILDMOSFET进行了开态输出特性模拟,输出特性曲线没有曲翘现象和负导现象,开态击穿电压可达到1 6V,器件有源区的温度降低了50℃.结构优化有利于提高器件性能和降低器件的开发成本. 相似文献
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50nm SOI-DTMOS器件的性能 总被引:1,自引:0,他引:1
利用二维器件模拟软件ISE对5 0nm沟道长度下SOI DTMOS器件性能进行了研究,并与常规结构的SOI器件作了比较.结果表明,在5 0nm沟长下,SOI DTMOS器件性能远远优于常规SOI器件.SOI DTMOS器件具有更好的亚阈值特性,其亚阈值泄漏电流比常规SOI器件小2~3个数量级,从而使其具有更低的静态功耗.同时,SOI DTMOS器件较高的驱动电流保证了管子的工作速度,并且较常规SOI器件能更有效地抑制短沟道器件的穿通效应、DIBL及SCE效应,从而保证了在尺寸进一步减小的情况下管子的性能.对SOI DTMOS器件的物理机制进行了初步分析,揭示了其性能远优于常规结构的物理本质 相似文献
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王文廉 《固体电子学研究与进展》2013,33(3)
非平衡超结器件的电荷补偿能力在薄层SOI器件中受到限制,文中提出一种具有T型电荷补偿区的器件结构。通过漏端刻蚀的PSOI结构使硅衬底与埋氧层同时参与纵向耐压,可以提高非平衡超结n区的电荷补偿能力;在埋氧层刻蚀区增加垂直的n型补偿区,弥补埋氧层的缺失。由横向的非平衡超结n区和漏端垂直的n区共同构成T型补偿区,可以有效缓解薄层SOI超结器件中的衬底辅助耗尽效应,优化横向电场,提高器件的耐压。器件的制作可以通过改进传统的PSOI工艺实现,应用于SOI功率集成电路。三维器件仿真结果表明,新结构下的器件耐压达到290V,相对于常规的SOI超结器件和非平衡超结器件提高了267%和164%。 相似文献
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Mohammad K. Anvarifard 《International Journal of Electronics》2013,100(8):1394-1406
A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications. 相似文献
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Jiang Yongheng Luo Xiaorong Li Yanfei Wang Pei Fan Ye Zhou Kun Wang Qi Hu Xiarong Zhang Bo 《半导体学报》2013,34(9):094005-5
A novel CMOS-compatible thin film SOI LDMOS with a novel body contact structure is proposed. It has a Si window and a P-body extended to the substrate through the Si window, thus, the P-body touches the PC region to form the body contact. Compared with the conventional floating body SOI LDMOS(FB SOI LDMOS) structure, the new structure increases the off-state BV by 54%, decreases the specific on resistance by 20%, improves the output characteristics significantly, and suppresses the self-heating effect. Furthermore, the advantages of the low leakage current and low output capacitance of SOI devices do not degrade. 相似文献
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随着微电子技术进入纳米领域,功耗成为制约技术发展的主要因素,因此,低功耗器件成为半导体器件领域的研究热点。负电容场效应晶体管基于铁电材料的负电容效应可有效地降低器件的亚阈值摆幅,从而降低器件的功耗。该文设计了一种基于绝缘体上硅(SOI)结构的铁电负电容场效应晶体管,利用TCAD Sentaurus仿真工具对负电容晶体管进行仿真研究,得到了亚阈值摆幅为30.931 mV/dec的负电容场效应晶体管的器件结构和参数。最后仿真研究了铁电层厚度、等效栅氧化层厚度对负电容场效应晶体管亚阈值特性的影响。 相似文献
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In this paper a novel structure for silicon on insulator metal semiconductor field effect transistors (SOI MESFETs) is proposed. The proposed structure contains two symmetrical oxide boxes at both sides of gate metal and extended drift region into the buried oxide which is named SO-ED-SOI-MESFET. SO-ED stands for symmetrical oxide boxes and extended drift region. DC and radio frequency characteristics of the SO-ED are analyzed by 2-D numerical simulation and compared with conventional SOI MESFET (C-SOI MESFET) characteristics. The obtained results demonstrate the superiorities of the proposed structure over C-SOI MESFET including increased breakdown voltage, higher driving current and improved RF characteristics. The extended drift region improves the current capability by increasing the effective channel thickness. The oxide region boosts the breakdown voltage due to its high tolerable electric field. Also, RF performance of the device is enhanced because of modified gate-source and gate-drain capacitances in the proposed structure. Unilateral power gain, maximum available gain and current gain experience 63, 52 and 63.5% improvement by applying the proposed structure, respectively. Thus the proposed structure can be considered as a proper candidate for using in high power and high frequency applications. 相似文献
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This work reports a novel SOI MESFET including silicon N-type and P-type wells inside the drift and buried oxide regions. The drift-diffusion equations along with the main physical models such as impact ionization, Shockley-Read-Hall and self-heating effect are carefully solved inside the structures. Modification of the potential profile occurs in the channel region and results in decrease in peak electric field. Output power density is successfully boosted owing to improved driving current and breakdown voltage, simultaneously. In addition, self-heating effect is alleviated in the proposed structure due to decreased effective thermal resistance of the channel region. Comprehensive DC and AC performance comparisons show that the proposed device promises a more reliable candidate than the conventional SOI structure for high voltage applications. 相似文献
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This paper presents the first results of a practical SOI LDMOSFET in patterned SOI substrate that has been successfully prepared by masked SIMOX method. The device exhibits good electrical performance including a leakage current of 20 nA, the flat output characteristic curves, a cutoff frequency up to 8 GHz, and a voltage gain of 2.5 dB at 2 GHz. The proposed technology not only suppresses floating body effects effectively but also preserves SOI technology’s advantage of low power assumption. Moreover, the process is compatible with conventional SOI technology. 相似文献