用于蓝牙收发机的低电压CMOS Gilbert混频器

对已报道的Gilbert混频器工作在低电压时存在的问题进行了分析,在此基础上,描述了利用改进的低电压设计技术,用于2 .4 GHz蓝牙收发机的上混频器/下混频器的设计.利用适用于低电压工作的负反馈与电流镜技术提高上混频器的线性度;而通过采用折叠级联输出,增加了低电压时下混频器的设计自由度,从而降低了噪声,提高了转换增益.基于0 .35μm CMOS工艺技术,在2 V电源电压下,对电路进行了仿真.结果表明:上混频器消耗的电流为3m A,输入三阶截距点达到2 0 d Bm ,输出的信号幅度为87m V;下混频器消耗的电流为3.5 m A,得到的转换增益是2 0 d B,输入参考噪声电压是6     

2.45 GHz有源标签接收机中的下变频混频器

设计了一种用于2.45 GHz有源标签接收机的低中频正交下变频混频器。改进了传统的吉尔伯特结构, 采用了共享跨导正交结构和电流注入技术, 以提高混频器的增益, 减小混频器的噪声。该混频器采用UMC 0.18 μm CMOS工艺设计。仿真结果表明, 该混频器在1.8 V电压下, 电流消耗为3.1 mA, 转换增益为17.18 dB, 输入1 dB压缩点Pin-1dB与输入3阶截点IIP3分别为-13.5 dBm, -3.23 dBm, 在2 MHz中频下的噪声系数为14 dB。     

一种0.9V低电压低本振功率CMOS有源混频器

设计了一种可工作于0.9 V低电压和-5 dBm本振功率的CMOS有源混频器.通过在MOS管栅极和衬底间引入耦合电容,利用衬底效应加快MOS管的导通和截止,使开关对的开关状态更理想,有效地降低混频器的噪声并提高其线性特性.采用0.18 μm CMOS工艺设计,在2.45 GHz本振信号和2.44 GHz射频信号输入下,实验结果表明该混频器可有效地实现混频且具有较好的性能指标:电压转换增益为12.4 dB,输入三阶截断点为-0.6 dBm,输入1dB压缩点为-3.4 dBm,单边带噪声系数为12 dB.     

2.4GHz 0.35μm CMOS Gilbert下变频器

利用0 35μm CMOS工艺实现了一种用于低中频接收机的Gilbert型下变频器.其中,混频器的输出级采用折叠级联输出,射频信号、本振信号和中频信号的频率分别为2 452GHz,2 45GHz和2MHz.测试表明:在3 3V电源电压条件下,整个混频器电路消耗的电流约为4mA,转换增益超过6dB,输入1dB压缩点约为-11dBm.     

一种2.4GHz 0.35μm CMOS Gilbert下变频器

利用0.35μm CMOS工艺实现了一种用于低中频接收机的Gilbert型下变频器.其中,混频器的输出级采用折叠级联输出,射频信号、本振信号和中频信号的频率分别为2.452GHz,2.45GHz和2MHz.测试表明:在3.3V电源电压条件下,整个混频器电路消耗的电流约为4mA,转换增益超过6dB,输入1dB压缩点约为-11dBm.     

一种低噪声高线性度CMOS上变频混频器

设计实现了一种采用开关跨导型结构的低噪声高线性度上变频混频器,详细分析了电路的噪声特性和线性度等性能参数,本振频率为900 MHz。芯片采用0.18μm Mixed signal CMOS工艺实现。测试结果表明,混频器的转换增益约为8 dB,单边带噪声系数约为11 dB,输入参考三阶交调点(IIP3)约为10.5 dBm。芯片工作在1.8 V电源电压下,消耗的电流为10 mA,芯片总面积为0.63 mm×0.78 mm。     

CMOS低功耗3-5GHz超宽带接收机射频前端

本文介绍了一种新的低功耗射频接收机前端, 适用于3-5GHz的超宽带系统. 基于0.13µm CMOS工艺实现, 该直接转换式接收机由宽带噪声抵消结构的跨导输入级, 正交无源混频器和跨阻负载放大器组成. 测试结果显示该接收机在整个3.1-4.7GHz 频带范围内的输入反射系数小于-8.5dB, 转换增益27dB, 噪声系数4dB, 输入三阶交调点-11.5dBm, 输入二阶交调点33dBm. 工作在1.2V电源电压下, 整个接收机共消耗18mA电流, 其中包括10mA用于片上正交本振信号产生和缓冲电路.芯片面积为1.1mm×1.5mm.     

一种2.4GHz 0.35μm CMOS Gilbert下变频器

利用0.35μm CMOS工艺实现了一种用于低中频接收机的Gilbert型下变频器．其中,混频器的输出级采用折叠级联输出,射频信号、本振信号和中频信号的频率分别为2.452GHz,2.45GHz和2MHz．测试表明：在3.3V电源电压条件下,整个混频器电路消耗的电流约为4mA,转换增益超过6dB,输入1dB压缩点约为－11dBm．     

一种电流注入式零中频正交混频器

设计了一种用于900MHz RFID阅读器的零中频正交下变频混频器,该混频器采用共跨导级正交结构,并利用电流注入技术减小噪声,在UMC0.18μmCMOS工艺下实现。整个芯片分为三部分,混频器、带隙基准以及缓冲器,总面积为1.1mm2。混频器在1.8V电压下消耗电流3.7mA,带宽范围880～940MHz,增益16.42dB,三阶截点为-4.625dBm,在100kHz处噪声系数为15.2dB。芯片能够达到阅读器的性能要求。     

高增益高线性度CMOS偶次谐波混频器设计

设计了一种能应用于GPS接收机的偶次谐波混频器,在RF输入端采用了电流复用电路提高混频器的转换增益和线性度,在LO输入端采用了倍频技术.同时,该拓扑结构还具有低功耗的优点.仿真结果表明:在1.8V电源电压下,RF频率1.575GHz,LO频率0.7895 GHz,LO功率为-5 dBm时,该混频器的转换增益为20.848 dB,三阶交调截至点为-2.297 dBm.表现出了高增益、高线性度的性能.     

一种高性能宽带直接变频射频前端设计

提出一种宽带(250 MHz~4.7 GHz)无电感BiCMOS射频前端结构,包含低噪声跨导放大器(LNTA)、带电阻无源混频器和跨阻级。低噪声跨导放大器使用了噪声和线性度消除技术,例如输入交叉耦合结构、互补输入和电流复用技术。带电阻无源混频器采用退化电阻来提高线性度。仿真结果表明, 当电源电压为3.3 V时,总电流为9.38 mA, 噪声系数为9.8 dB(SSB),电压转换增益为20 dB,输入3阶交调为+11.8 dBm。     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.     

Body effect up- and down-conversion mixer circuits for low-voltage ultra-wideband operation

This article presents fully differential up- and down-conversion mixer circuits manufactured in a triple well 45 nm CMOS process for low-voltage Ultra-Wideband transmitter and receiver applications. The proposed circuits both employ the transistor bulk terminal for signal injection. While the down-conversion mixer uses the bulk for switching via threshold voltage modulation, the up-conversion mixer applies the baseband signal to the bulk, thereby implicitly incorporating the back-gate controlled current source of the MOS transistor. Both circuits offer resistive on-chip termination and DC coupled output buffering for measurement purposes. The down-conversion mixer features an input-referred compression point of −13.2 dBm and a maximum conversion gain of 9.4 dB at 2.5 GHz with the 3-dB corner frequency being beyond 10 GHz. The implemented up-conversion mixer offers a maximum conversion gain of −8.8 dB at 5.8 GHz together with an output-referred compression point of −9.7 dBm. The operational bandwidth ranges from 4.5 to 6.7 GHz. Both circuits operate at a low supply voltage of 1.1 V.     

一种用于超高频RFID阅读器的正交下变频混频器的分析与设计

分析了共用跨导级的正交下变频混频器的性能,包括电压转换增益、线性度、噪声系数和镜象抑制比,分析表明其在电流开关模式下比传统的Gilbert混频器对具有更好的性能.设计并优化了一个基于共用跨导级结构的用于超高频RFID阅读器的正交下变频混频器.在915MHz频段上,该混频器测得12.5dB的转换增益,10dBm的IIP3 ,58dBm的IIP2和17.6dB的SSB噪声系数.芯片采用0.18μm 1P6M RF CMOS工艺实现,在1.8V的电源电压下仅消耗3mA电流.     

一种新型的基于GSM1900标准的1.9GHz CMOS混频器

介绍了一种0.18μm CMOS工艺基于GSM1900(PCS1900)标准低中频接收机中的混频器.该混频器采用了一种新型的折叠式吉尔伯特单元结构.在3.3V电源电压、中频频率为100kHz的情况下,该混频器达到了6dB的转换增益,18.5dB的噪声系数(1MHz中频)和11.5dBm IIP3的高线性度,同时仅消耗7mA电流.     

2.4GHz带片上非平衡变压器射频前端的设计与优化

本文介绍了一种工作在2.4GHz频段的低功耗、低噪声、高线性射频接收机前端电路,该接收前端电路使用新型的带三种增益模式的LNA,并提出一种新的片上非平衡变压器优化技术。前端电路采用了直接变频结构,使用片上非平衡变压器实现低噪声放大器与下变频混频器之间的单端-差分转换,优化设计以提高前端电路的噪声性能。本文使用锗硅0.35um BiCMOS工艺,所采用的技术同样适用于CMOS工艺。前端电路总的最大转换增益为36dB;在高增益模式下的双边带噪声系数为3.8dB;低增益模式下,输入三阶交调点位12.5dBm。为了获得最大的输入动态范围,低噪声放大器采用三种可调增益模式,低增益模式使用by-pass结构,大大提高了大信号输入下接收前端的线性度。下变频混频器在输出端使用可调R-C tank,滤除带外高频杂波。混频器输出使用射极跟随器作为输出极驱动片外50ohm负载。该接收前端在2.85-V电源供电下,功耗为33mW,芯片面积为0.66mm2。     

应用于802.11b无线局域网的低噪声高线性度的CMOS射频接收机

实现了一个单片集成、直接转换结构的2.4GHz CMOS接收机.这个正交接收机作为低成本方案应用于802.11b无线局域网系统,所处理的数据传输率为该系统的最大速率--11Mbps.基于系统设计以及低噪声高线性度考虑,设计了低噪声放大器、直接转换混频器、增益可变放大器、低通滤波器、直流失调抵消电路及其他辅助电路.该芯片采用中芯国际0.18μm 1p6m RF CMOS工艺流片.所测的接收机性能如下:噪声系数为4.1dB,高增益设置下低噪声放大器与混频器的输入三阶交调点为-7.5dBm,整个接收机的输入三阶交调点为-14dBm,相邻信道干扰抑制能力在距中心频率30MHz处达到53dBc,输出直流失调电压小于5mV.该接收机采用1.8V电源电压,I,Q两路消耗的总电流为44mA.     

A Low Voltage Mixer With Improved Noise Figure

A 5.2 GHz low voltage mixer with improved noise figure using TSMC 0.18 $mu$m CMOS technology is presented in this letter. This mixer utilizes current reuse and ac-coupled folded switching to achieve low supply voltage. The noise figure of the mixer is strongly influenced by flicker noise. A resonating inductor is implemented for tuning out the parasitic components, which not only can improve noise figure but also enhance conversion gain. A low voltage mixer without resonating technique has also been fabricated and measured for comparison. Simulated results reveal that flicker corner frequency is lowered. The measured results show 4.5 dB conversion gain enhancement and 4 dB reduction of noise figure. The down-conversion mixer with resonating inductor achieves 5.8 dB conversion gain, ${-}16$ dBm ${rm P}_{{rm 1dB}},$ ${-}6$ dBm ${rm IIP}_{3}$ at power consumption of 3.8 mW and 1 V supply voltage.      

A Low-Noise WLAN Mixer Using Switched Biasing Technique

A low-noise CMOS down-conversion mixer for WLAN applications is presented in this letter. The proposed mixer is based on the conventional Gilbert-type topology with switched biasing technique for a current source instead of static biasing, which lowers noise over a wide range of frequencies. Moreover, a dc level shifter is used for the symmetric switching operation in tail current transistors. A current bleeding technique is adopted to reduce the noise caused by the LO switching operation. The proposed mixer was fabricated using a 0.18 mum 1P6M CMOS process. Measurement results include a conversion gain of 7.5 dB, an IIP3 of -5 dBm, and noise figures of 10.9 dB at 1 MHz and 7.6 dB at 100 MHz. The mixer core consumes a current of 4.5 mA from a supply voltage of 1.8 V. The chip size, including pads for measurements, is 0.88 times 0.88 mm².