RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time     

Prescaled clock recovery based on small timing misalignment of datapulses

A simple and robust prescaled clock recovery technique is analyzed and demonstrated. An electrical clock is extracted from an ultra-high-speed time-division multiplexed (TDM) RZ signal using a “classic” approach to clock recovery with a detector and a bandpass filter (BPF). A subharmonic tone at the base rate frequency is generated by inducing a small misalignment between adjacent pulses in the transmitted data. The subharmonic tone is recovered as a clock signal at the receiver. Numerical calculations clarify the effect of filter bandwidth, word length, and strength of timing shift on the received timing jitter. Furthermore, it is found numerically that correlated TDM channels will decrease the jitter of the recovered clock considerably. A clock recovery circuit is implemented into an experimental 40 Gb/s and 80 Gb/s optical TDM (O-TDM) system without any observed penalty. Measurements of the timing jitter of the recovered prescaled clock have been performed to verify the numerical results. A 10 GHz clock signal with subpicosecond root-mean-square timing jitter is recovered from a 40-Gb/s O-TDM sequence without a phase-locked loop (PLL) configuration. By using a PLL-configuration, the timing jitter is reduced further by 50%. A discussion on the influence on transmission capacity is performed in general and for nonlinear optical communication systems in particular     

A 30-MHz hybrid analog/digital clock recovery circuit in 2-μmCMOS

A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 95% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 p.p.m./°C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW, and the active area is 30000 mil² in a 2-μm single-poly double-metal n-well CMOS process     

A CMOS STI-Bound Single-Photon Avalanche Diode With 27-ps Timing Resolution and a Reduced Diffusion Tail

Single-photon avalanche diodes (SPADs) measure individual photons' time of arrival. Low detector jitter is required in many SPAD applications. This letter describes a method for significantly reducing SPAD jitter using an area-efficient shallow-trench-isolation guard ring. The structure prevents lateral drift and diffusion of charge carriers, resulting in improved timing resolution. Experimental results of the device, fabricated in a 0.18- $muhbox{m}$ CMOS technology, are presented. The timing resolution of the SPAD is 27-ps full-width at half-maximum. Importantly, the diffusion tail exhibits only 96-ps full-width at hundredth-maximum, a three times improvement over previously published SPAD results. The reduced jitter can be translated to improved bit error rates in quantum key distribution systems, faster bit rates in pulse position modulation optical links, and greater contrast in high-resolution fluorescence lifetime imaging microscopy.      

The effect of timing jitter on the performance of a discretemultitone system

The transmission of high-speed data over severely band-limited channels may be accomplished through the use of discrete multitone (DMT) modulation, a modulation technique that has been proposed for a number of new applications. While the performance of a DMT system has been analyzed by a number of authors, these analyses ignore the effect of timing jitter on system performance. Timing jitter becomes an increasingly important concern as higher data rates are supported and larger constellations are allowed on the DMT subchannels. Hence, in this paper, we assume that synchronization is maintained by using a digital phase-locked loop to track a pilot carrier, Given this model, we derive error rate expressions for an uncoded DMT system operating in the presence of timing jitter, and we derive an expression for the interchannel distortion that results from a varying timing offset across the DMT symbol. In addition, we investigate the performance of trellis-coded DMT modulation in the presence of timing jitter. Practical examples from the asymmetric digital subscriber line (ADSL) service are used to illustrate various results     

Timing Recovery in Digital Subscriber Loops Using Baud-Rate Sampling

Sampled-data techniques are the most practical means of obtaining the necessary signal processing functions for timing recovery in the VLSI implementation of a digital subscriber loop transceiver. The sampled-data timing recovery techniques described in this paper are applicable to both echo cancellation and time-compression multiplexing systems. Timing recovery using baud-rate sampling in conjunction with a special pulse-shaping and timing function fulfills all the objectives for timing recovery in this application. It recovers a timing phase that has minimum precursor intersymbol interference, and makes possible the combination of decision feedback equalizer and echo canceler, reducing the convergence time and increasing the step size. The pulse-shaping function can be performed either in the transmitter by means of digital coding, or in the receiver by means of analog filtering. In the latter case, the transmitted pulse is compatible with more conventional approaches. The proposed partial-response line coding, a special form of AMI coding, is less susceptible to line impairments if detected as a two-level signal. Performance by analysis, simulation, and experimental measurements is reported on a variety of cable configurations, some including bridged taps. Analysis of jitter performance leads to design techniques for reducing the jitter magnitude.     

A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver

A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78% relative to pure Vernier delay line structure with a wide measurement range. The counter circuit occupies an area of 19 $mu$ m $times$ 61 $mu$ m in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The power supply rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. The core circuit occupies an area of only 0.5 mm $times$ 0.15 mm with the 90-nm CMOS process. The Gaussian and uniform distributions jitter is verified at a 5-ps timing resolution and a 2.5-GHz input clock frequency .      

A 900-Mb/s CMOS data recovery DLL using half-frequency clock

A data recovery delay-locked loop (DILL) for nonreturn-to-zero (NRZ) data transmission is described. A reference clock is delayed for triggering a latch that samples the incoming NRZ data stream. The data rate can be twice the reference clock frequency. The circuit has a proportional nondead-zone sampling phase detector that also serves the role of charge pump. A self-correcting function reduces the problem of the finite phase capture range associated with conventional DLLs. The prototype circuit is fabricated in 2.5-V 0.25-μm CMOS and occupies an area of only 270 × 50 μm². It is demonstrated that at 900-Mb/s NRZ data, jitter is reduced from 118.2- to 31.3-ps rms jitter for a power consumption of only 3 mW     

The Zipper prototype: a complete and flexible VDSL multicarrier solution

This article presents the prototype developed to prove the Zipper concept and contribute to VDSL standardization. This solution includes the hardware and software needed to demonstrate that the VDSL multicarrier is a feasible, flexible, high-performance, competitive solution. The prototype provides the network management and telemetry software needed to simplify system setup and performance evaluation, respectively. It includes two interfaces: one to plug a twisted pair cable or a cable simulator, and the other to connect the ATM transport protocol. A 155 Mb/s (OC-3 rate) ATM-SDH/SONET interface is provided too. The first measurements performed between two VDSL modems, with injected noise of 20 VDSL equivalent lines, show that it is possible to transmit (in downstream and upstream directions) payload bit rates up to 48 Mb/s at 300 m and up to 25 Mb/s at 1500 m using 0.5 mm copper cables. The prototype has been designed using a modular and flexible architecture able to allow future VDSL modem extensions. The reuse of this prototype is expected for other applications where OFDM technology applies.     

Analog timing recovery for a noise-predictive decision-feedback equalizer

A timing recovery architecture and its CMOS implementation are described for a noise-predictive decision-feedback equalizer (NPDFE). The 0.5-/spl mu/m CMOS prototype includes timing recovery and the NPDFE and operates at 160 Mbit/s. The timing recovery blocks dissipate 27 mW from 3.3 V, occupy 0.2 mm/sup 2/, and achieve a root mean square jitter of 50 ps, which is 0.8% of a bit period.     

Timing Jitter Effects on Digital Subscriber Loop Echo Cancellers: Part II--Considerations for Squaring Loop Timing Recovery

The performance of an adaptive echo canceller at the looptimed subscriber end of a digital subscriber loop has been shown to be sensitive to jitter arising from the timing recovery subsystem. We evaluate this degradation for the common timing recovery subsystem consisting of a prefilter, a squarer, and a second-order phase-locked loop. The evaluation shows the influence of equalization, prefilter shape, and phaselocked loop parameters. A narrow-band accurately tuned prefilter, line equalizer, and a narrow-band phase-locked loop are found to be necessary for adequate performance in a 144 kbit/s bipolar-coded digital subscriber loop system employing echo cancellation.     

Simulation Studies on Nonlinear Bit Synchronizers in APD-Based Optical Receivers

This paper examines the problem of self bit synchronization employing nonlinear timing extraction schemes in optical receivers with avalanche photodetectors (APD) through digital computer simulation. A direct algorithm is developed for the simulation of sample functions of the APD output process with due consideration to intersymbol interference (ISI). Simulation of all the functional blocks used for synchronization is carried out in the discrete time domain. Performances of the nonlinear timing recovery schemes are evaluated in terms of the rms timing jitter for nonreturn-to-zero (NRZ) as well as return-to-zero (RZ) signaling formats.     

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

Digital filter and square timing recovery

The digital realization of timing recovery circuits for digital data transmission is considered. A digital algorithm is proposed that can be implemented very efficiently even at high data rates. The resulting timing jitter has been computed and verified by simulations. In contrast to other known algorithms, the one presented here allows free-running sampling oscillators and a novel planar filtering method that prevents synchronization hangups     

A picosecond-accuracy, 700-MHz range, Si bipolar time intervalcounter LSI

A picosecond-accuracy digital vernier-based single-chip time interval counter (TIC) LSI applicable to timing calibration in state-of-the-art high-speed LSI test systems is described. Jitter performance is improved to three times higher than in conventional circuitry by using a new skew detection circuit that is insensitive to the jitter caused by metastable transitions in flip-flops. All the hardware except the signal sources has been integrated on a Si bipolar 2.5 K gate array LSI by developing fully digitally processes heat-signal and trigger control circuits. The chip is mounted on a dedicated ceramic package employing coplanar lines with a 3-GHz bandwidth. Overall performance achieves 2.3-ps standard deviation, ±3-ps linearity, zero-skew offset of ±2.7 ps, and an equivalent input slew time of 33.6 ps/V at input clock rates up to 700 MHz     

All-Optical Clock Recovery for 40-Gb/s MZM-Generated NRZ-DPSK Signals Using a Self-Pulsating DBR Laser

All-optical clock recovery for the nonreturn-to-zero differential phase-shift-keying (NRZ-DPSK) modulation format is demonstrated experimentally at 40 Gb/s using a self-pulsating distributed Bragg reflector laser. The use of a Mach–Zehnder modulator to generate the NRZ-DPSK signal yields a modulated signal spectrum with a weak clock tone. The self-pulsating laser is able to directly recover a clock signal with a root-mean-square timing jitter of 760 fs and an extinction ratio of 13 dB; a preprocessing stage to enhance the clock tone is not required. The timing jitter of the recovered clock signal is characterized for different values of the input signal optical signal-to-noise ratio and for varying amounts of waveform distortion due to polarization-mode dispersion.      

All-Optical NRZ-DPSK Clock Recovery Using Chromatic-Dispersion-Induced Clock Tone

All-optical clock recovery (CR) from 10-Gb/s nonreturn-to-zero differential phase-shift-keying (NRZ-DPSK) signal is demonstrated experimentally by introducing the chromatic-dispersion-induced clock tone into a free-running semiconductor optical amplifier (SOA)-based fiber ring laser for achieving mode-locking. Since no special component is required for NRZ-DPSK demodulation, our proposed method is very promising because of its simple configuration and better stability. The good performance of our proposed configuration is fulfilled with a 20-km standard single-mode fiber to regenerate clock tone of the NRZ-DPSK signal. The recovered clock signal with the extinction ratio of 17 dB and the root-mean-square timing jitter of 718 fs is achieved under 2³¹-1 pseudorandom binary sequence NRZ-DPSK signals measurement     

Performance of a 51.84-Mb/s VDSL transceiver over the loop withbridged taps

This paper presents a study of the effects of bridged taps on very high-speed digital subscriber line (VDSL) transmission systems. It is shown that the short bridged taps, which affect VDSL signals, are much more damaging than the longer bridged taps, which affect other xDSL signals, such as high-rate digital subscriber line (HDSL) and asymmetric digital subscriber line (ADSL). Specifically, short bridged taps introduce a lot of linear distortion in the loop's transfer function. In addition, they also tend to introduce more overall propagation loss than longer bridged taps. The peak-power-to-average-power ratio (PAR) of the signal increases for the loop with short bridged taps, and thus more A/D bits are needed in the implementation of a digital VDSL transceiver as compared to the loop with long bridged taps. The performance of various equalizer structures is discussed in the presence of a severe channel distortion caused by the bridged tap     

Fiber-Optic Hybrid Digital Transmission System Experiment

The hybrid digital transmission system, involving 2Rrepeaters between 3R (Reshaping, Retiming and Regenerating)-repeaters, is a suitable system for fiber-optic transmission. The 2R (Reshaping and Regenerating)-repeatered line enables bit rate free transmission, but cannot suppress the accumulated timing jitter in transmitting pulse streams. The trial 1-8 Mbit/s transmission system, using step-index multimode fibers and light emitting diodes, was designed and tested. Multirepeater transmission experiments using optical fiber cable laid in an underground cable tunnel were also performed. The timing jitter accumulations were measured through the multi-repeatered line. Measured timing jitter values were in good agreement with theoretical values. Experimental results show satisfactory feasibility of a fiberoptic hybrid digital transmission system using step-index or gradedindex multimode fibers.     

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/spl mu/m CMOS process with core area of 0.16 mm/sup 2/. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.