对寄生电容不灵敏的开关电容有源滤波器的设计

采用单位缓冲器设计对寄生电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件，利用该元件对椭圆函数式LC低通滤波器进行SC模拟。为了获得电容最佳值，提出了一种简单的最优化方法；并采用寄生电阻预畸变与SC负电阻相结合的办法，设计的SC滤波器对寄生电容不灵敏，且电路简单。在电子工作平台(EWB)上进行五阶椭圆低通SC-FDNR滤波器仿真，测量数据最大相对误差为0．948％，仿真结果表明该方法实用可行，效果明显。     

使用单位增益缓冲器构成的抗寄生SC跨导

用单位增益缓冲器构成的开关电容滤波器(SCF),若能消除寄生电容引起的阻性寄生,则可用于高频设计,总寄生灵敏度会因此大大降低。本文在此基础上提出一种新的抗寄生开关电容(SC)跨导元件电路差分跨导元件,并用它构成了适用于高频的SC浮地电感和积分器。最后用它实现了一个三阶椭圆函数低通滤波器,并经计算机模拟和实验验证,证明了该方案的正确性。     

减小SC滤波器中GB效应的新结构

本文讨论了在开关电容(SC)滤波器中如何减少增益带宽积(GB)效应的问题,提出了一个减少GB效应的新的双二次拓扑结构,此结构对寄生电容不敏感,并且具有很低的无源W0,Q灵敏度。以低通SC滤波器为例,给出了减小GB效应的具体设计方法。并用设计实例和实验结果证明了所得结论的正确性。     

开关电容滤波器的浮地电压反向开关及浮地电感的新实现

本文介绍在具有电压反向开关(VIS)的开关电容(SC)滤波器中,电感模拟电路的新设计方法。浮地电感和浮地VIS能同时实现。该电路对于底片寄生电容很不敏感,并且完全保持了VIS-SC滤波器所特有的良好敏感性。作为例子,本文给出了一个具有浮地电感的5阶椭圆低通滤波器,实验结果与理论相符。     

RC有源滤波器的计算机仿真设计

<正> 集中参数RC有源滤波器的传统人工设计方法在设计时颇费工夫,由于情况的复杂性,往往所得的滤波器的元件数目并不是最节省的,其特性也并不是最理想的。本文所述的设计方法,是直接从工程上预给的特性要求出发,由计算机按一定的步骤自动地准确地给出,能满足工程要求的集中参数RC有源滤波器的特性及元件的数值。由于可进行计算机的频率扫描仿真,根据仿真描绘出来的频率响应曲线,可随时对不满意的参数进行修改,屏幕立即显示出新的频率响应曲线,不断地重复该过程直到满意时为止。这样,设计的结果非常直观,得出的滤波器的元件数目最少、特性最理想,而所费的工夫却很少。该方法是在假设滤波器中的元器件为理想的情况下(即假设电阻R为纯电阻、电容C为纯电容、运算放大器为理想的放大器)进行设计的,因此在实际工作频率太高时,设计误差可能过大。如果选择的运算放大器其最高工作频率远远大于实际工作频率,则在设计工作频率为1MHz以下的滤波器时,一般情况下其工作误差均能够满足实际工程的需要。     

偶数阶电流模椭圆滤波器的综合设计

本文提出了一种基于MOCCII的任意偶数阶电流模椭圆滤波器综合设计方法。通过对n阶(偶数)椭圆传输函数进行分析,将其分解成一系列能用无损积分器实现的表达式;并对输出电流信号进行线性组合,以实现了偶数阶的电流模式椭圆滤波器的综合。该方法实现的电路结构简单,所用有源和无源元件最少,仅由n个接地电容,(3n-1)/2个有源器件和接地电阻构成。给出了四阶高通、低通和带通椭圆形滤波器的设计实例。Pspice仿真结果表明采用该方法设计偶数阶电流模式椭圆滤波器是可行的,适用的。     

CCC Ⅱ模拟电感的非理想特性分析及应用

提出了利用理想第二代电流控制传输器(CCC II)模拟电感特性的结构。分析了基于CCC II模拟电感的理想电感效应有效范围、主要寄生电容电阻的影响及其补偿方法,给出了模拟电感特性仿真结果。在此基础上,对5阶巴特沃斯(Butterworth)高通滤波器进行综合。电路具有结构简单、集成度高,截止频率连续可调等优点。仿真结果证明了设计的正确性。     

荷控忆阻器记忆衰退的寄生效应

荷控忆阻器在寄生元件存在的情况下,可能发生记忆衰退现象。该文采用忆阻器动力学路线图和仿真的方法,研究了忆阻器寄生电阻和寄生电容对其动力学特性的影响。理论和仿真分析发现,理想荷控(流控)忆阻器在直流和交流激励下,寄生电阻或寄生电容单独存在时不发生记忆衰退现象,但在寄生电阻和寄生电容同时存在的情况下会发生记忆衰退,其机理是寄生元件形成放电通路,从而导致荷控忆阻器产生了记忆衰退。     

开关电流椭圆低通滤波器的设计

通过实例,提出了由５阶ＲＬＣ椭园低通滤波器原型电路到相应的有源ＲＣ滤波器电路,再到开关电容滤波器电路及开关电流滤波器的设计,设计方法简单易行,由于分立元件的ＲＬＣ椭园低通滤波器的归一化电路及其参数有表册可表,可以很容易地设计出所需性能的ＲＬＣ滤波器,据此也可以很方便地设计出具有各种所需性能参数的开关电流滤波器,这在采样数据信号处理中是十分是用的。     

同轴腔体窄带带通滤波器快速设计方法

为了满足卫星用滤波器研制周期短、可靠性高的要求,提出了一种快速设计经典同轴腔体滤波器的方法.该方法通过原型滤波器查表可以计算滤波器节数、耦合常数、群时延、单腔谐振频率、单腔Q值等初始值;通过使用三维电磁(EM)仿真软件得到单腔调谐钉长度和加载电容值的对应关系、两个腔体间耦合系数及端口抽头高度等模型SnP参数;通过电路仿真软件使用集总元件对电容加载的量值进行优化,极大地提高了仿真的速度.最后使用该协同仿真方法设计一同轴腔体滤波器,并对仿真结果进行了验证.     

Integrated switched-capacitor FDNR filter

A switched-capacitor filter using a frequency-dependent negative resistance (FDNR) is described. FDNR filters closely simulate passive LC filters, thereby retaining passband stability and design simplicity. The filter has been implemented in LSI and designed to perform the transmit/receive filtering for PCM codecs. Circuits are described that overcome the floating node and floating amplifier problems previously associated with FDNRs.     

On the realization of the floating simulators using only grounded passive components

In this paper, two novel circuits for realizing floating inductance, floating capacitance, floating frequency dependent negative resistance (FDNR) and grounded to floating admittance converter depending on the passive component selection are proposed. Both of the proposed simulators employ second-generation current controlled conveyors (CCCIIs) and only grounded passive elements. The non-ideal current and voltage gain as well as parasitic impedance effects on the first proposed circuit are investigated. Also, simulation results using SPICE program are given for the first introduced floating simulator to verify the theory and to exhibit the performance of the circuit.     

FDCCII-based FDNR simulator topologies

In this article, three new circuits for realising frequency-dependent negative resistance (FDNR) are proposed. All proposed circuits employ a single fully differential current conveyor, grounded capacitors and resistor. Proposed circuits consist of minimum number of passive and active elements. All proposed circuits are lossless FDNR. The performance of the proposed FDNR is demonstrated on the third-order Butterworth low-pass filter. Simulation results are included to verify the theory.     

Design considerations for high-frequency crystal oscillators

The deleterious effects of crystal shunt capacitance and series resistance on the performance of series-mode oscillators are discussed. When the parasitic capacitance across the crystal significantly modifies the transconductance of the amplifying stage the circuits can become susceptible to a parasitic second mode of oscillation above the series-resonance frequency of the crystal. A simple model that can sufficiently describe such crystal oscillator circuits was developed and used to derive simple design equations that can accurately predict the behavior of these circuits. The design equations should be especially useful for a reliable design in cases when it is not practical to use an additional inductor to compensate for the parasitic shunt capacitance of the crystal. It is shown theoretically that the inclusion of this capacitance in the feedback path reduces the total effective capacitance in the tank circuit, which is tuned to the desired overtone frequency. This creates a second mode of oscillation frequency which is higher than the desired crystal resonance frequency. The ranges of loop-gain and tank resistance values that can prevent this parasitic mode of oscillations are derived. It is also shown that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance     

Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping

In this paper, a new grounded positive lossless frequency dependent negative resistance (FDNR) simulator and two of its applications are presented. The proposed FDNR uses single OTRA and requires five number of passive components; two resistances and three capacitances. The workability of the proposed simulator is demonstrated through the realization of a single resistance controlled oscillator (SRCO) and a fifth order elliptic filter. A detail non-ideality analysis is also done for both FDNR and SRCO. In addition the sensitivity, non-ideality effect and frequency stability analysis of SRCO have been presented. Monte Carlo simulation of the SRCO output has been given and discussed. Moreover, the layout of OTRA, FDNR and SRCO and their post layout simulations in 180 nm are given. PSPICE simulation and experimental results are included to verify theory.     

低截止频率多倍频程高增益对跖Vivaldi天线北大核心CSCD

针对传统对跖Vivaldi天线的最低截止工作频率较高、增益较低和方向性较差的问题,文中设计了一种新型超宽带对跖Vivaldi天线。融合运用辐射极板开矩形斜槽、加载吸收电阻和寄生矩形贴片等一系列电磁调控措施,扩展了天线的低频工作带宽;采取在天线极板间加载椭圆寄生贴片的技术方式大幅提高了天线的方向性和辐射增益。最后给出了天线的设计流程,从电场分布和表面电流分布的角度揭示了天线的微观工作机制。仿真和实测结果表明:天线的工作频带为0.85~16 GHz(近20倍频程),相对带宽达180%,在3 GHz以上频段增益均超过10 dBi,并且具有较好的端射方向性,在超宽带无线通信、雷达探测、电子对抗和遥感遥测等领域具有广泛的应用前景。     

改进EMI滤波器的高频寄生效应方法

针对滤波器小型化、轻型化、薄型化方向发展的趋势,介绍了平面集成滤波器的概念,通过比较分立元器件滤波器与集成滤波器的异同,分析分立元器件的高频寄生效应,介绍了平面PCB如何构建电感和电容及有效去除其高频寄生效应。并用MAXWELL软件对其仿真,得出其高频寄生参数。最后通过ADS软件对其高频寄生参数建模,验证了该方法是有效的。     

一种基于半分析法的HEMT小信号参数的提取方法

提出了一种基于半分析法的高速电子迁移率半导体晶体管小信号模型的提取方法.此方法是用测试结构的方法来提取焊盘电容和寄生电感,半分析法来提取寄生电阻,提高了寄生电阻的提取精度.在频率高达40 GHz的范围内,多偏置情况下模拟的S参数和测试的S参数曲线吻合良好,证明这种方法是正确的.     

Pi型电感耦合LTCC滤波器的寄生感性耦合研究

对二阶Pi型电感耦合LTCC滤波器中各个元件的电容及电感寄生效应进行了分析,提出了一种新的寄生电感耦合分析方法,并根据分析结果设计了一个二阶Pi型电感耦合和一个二阶Pi型电容耦合LTCC带通滤波器,其中,电感耦合滤波器的设计指标为:中心频率2.45GHz,相对带宽32.65%,带内插入损耗2dB,回波损耗18 dB;电...