数字信号与模拟信号的频谱分析及数字电视电平的测量

现各地有线电视网络都在进行数字化改造,网络调试中用户数字电平的调试是很重要的部分.同模拟电视信号电平一样,在有线数字电视系统中数字信号电平太高或太低对系统指标影响都很大.在用户端电缆信号系统出口处要求:信号电平为47～67 dBμV(比模拟电视信号的要求低10 dB),数字相邻频道间最大电平差为≤3 dB,数字频道与相邻模拟频道间最大电平差为≤13 dB.     

基于双电源系统的电荷泵电路设计

设计了一款应用于双电源系统中的电荷泵电路结构,通过内部电平转化与控制电路,在双电源系统中实现不同逻辑电平控制产生高压的目的,为EEPROM存储单元提供擦写所需高压.电路采用ZMOS管作为传输管,提高传输效率;在电荷泵不工作时,所有子电路关闭,实现零功耗设计.仿真结果显示,电路输出电压精度高、上电速度快、驱动能力强.电路采用SMIC 0.18μm CMOS工艺流片,已实际应用于数字电位计芯片设计中,输出高压稳定,达到设计要求,性能良好.     

基于CPLD的大屏幕扫描电路设计

为了能显示稳定的图像,对扫描电路的速度要求很高,特别是在实现灰度控制时,要求更高。所以,精心地设计扫描电路是提高图像稳定性的关键。介绍LED大屏幕显示电路结构及扫描电路的设计方法,给出Altera公司的EPM7128在大屏幕扫描电路中的设计实例,阐述可编程逻辑器件在高速数字系统应用中的优点。通过实验,扫描图像非常稳定,充分体现了可编程逻辑器件在高速复杂数学系统中的优势。     

电视音频系统中的电平概念及应用

随着广播电视系统数字化技术的快速发展,大量数字设备进入节目制作系统,与模拟设备混合使用.在系统连接及节目制作中,如何理解和应用电平概念,直接影响到节目制作的质量,本文介绍了数字与模拟电平概念的区别、如何设置正确的基准电平、以及提高节目制作质量的一些心得体会.     

有线数字电视传输特性与故障解析

1 数字电视传输系统的主要性能指标 在数字电视系统中,我们经常要测试和观察以下几项性能指标: (1)数字信号电平:数字频道的电平是用被测频道的平均功率来表达的,称为数字频道平均功率,测量的方法是对整个频道扫描、抽样,把每一个抽样的功率值取平均,然后在信道的带宽内进行积分,得到信道的平均功率,这种测量功能只有专用的数字信号测量仪器才能完成.     

有线数字电视传输特性与故障解析

1 数字电视传输系统的主要性能指标 　　在数字电视系统中,我们经常要测试和观察以下几项性能指标: 　　(1)数字信号电平:数字频道的电平是用被测频道的平均功率来表达的,称为数字频道平均功率,测量的方法是对整个频道扫描、抽样,把每一个抽样的功率值取平均,然后在信道的带宽内进行积分,得到信道的平均功率,这种测量功能只有专用的数字信号测量仪器才能完成.……     

一种新型轻量化扫描反射镜设计

根据反射镜轻量化的要求,从材料的选择、轻量化结构形式的确定以及支撑结构的设计三个方面对某机载IRST系统椭圆形扫描反射镜进行轻量化设计。经有限元分析表明,所设计的扫描反射镜在谐振频率、旋转变形、热变形等方面均能满足使用要求,结构设计合理可行。     

DAL嵌入SDI音频AGC和检测系统

产品概述 数字电视频道之间和节目之间声音响度的差异是数字节目制作和播出中的新问题，众多频道之间和不同节目之间的声音响度差别过大，在模拟时代就存在，但调节音量比较方便。节目数字化以后，在数字传送的中间环节变动数字音频电平比较困难。本系统就是使数字音量电平符合规格要求，稳定在一个标准电平或一个设定电平范围之内并自动监测的系统，并给出报警和记录。     

线阵激光雷达同步扫描系统的设计

为了实现线阵激光雷达的同步动态扫描,提出了一种提出对PIN光电二极管的输出基准信号进行电平转换驱动旋转平台,从而对三维景物实现推扫的方法。介绍了系统的硬件组成,设计了电平转换驱动电路,阐述了同步扫描系统的原理。实验表明,系统的结构紧凑,运行可靠,能在整个圆周范围内进行扫描,测量的精度高达。     

用于DRM接收机的信道估计算法

DRM(Digital Radio Mondial)规定了一种应用于30MHz以下地面广播的数字声音广播系统,能够高质量地传输声音、数据及静止图片等。DRM系统采用正交频分复用和多电平调制技术,为保证接收信号质量,在接收机中需要进行信道均衡。根据DRM系统发射信号的特点,设计了一种信道估计算法,兼顾了复杂程度和均衡精度,并且对载波频偏不敏感。     

数字系统的边界扫描设计技术及应用

用边界扫描设计技术可大大改善数字系统的可测试性。本文就边界扫描芯片及应用进行了探讨。     

基于MBSE的微波统一测控系统测试性设计

针对当前微波统一测控系统研制中存在的测试性要求宽松、测试性设计模式落后的问题,通过综合权衡可靠性、维修性和保障性的各项要求和约束条件,确定了微波统一测控系统的测试性定量要求,并对开展测试性定量设计和验证的可行性进行了论证;采用系统工程设计思想,将测试性设计和功能设计融合,构建了基于模型的系统工程（Model-based Systems Engineering,MBSE）的测试性设计环境和设计流程,可为微波统一测控系统在数字化研制过程中开展测试性设计和仿真验证提供参考。     

Ultra-fast CAD scan chain highlighting for failure analysis assistance

Automatic test pattern generation (ATPG) and scan tests are common design for testability methods (DfT) for digital logic ICs. A prerequisite for structural logic tests is the integrity of the embedded test circuit itself, i.e. the scan flipflops that are stringed together in scan chains. If there is a failure within one of the scan chains, localization can be quite challenging. One particular problem for failure analysis engineers is the CAD navigation along the chain: in order to display the physical position of a scan chain, hundreds or even thousands of flipflops have to be cross-mapped between the design netlist and the physical layout. This task requires extensive computing and can be very time-consuming. The work described in this paper is a new data processing method that reduces the required computing time from several hours down to a few seconds.     

A partial scan design unifying structural analysis and testabilities

To overcome the large extra hardware overhead attendant in full scan design, the concept of partial scan designs has emerged with the virtue of less area and testability close to full scan. Two typical partial scan techniques, based on structural analysis and testabilities, are widely adopted. The structural analysis requires less searching time, however in general the fault coverage is lower. On the other hand, the techniques using testabilities result in higher fault coverage, but require an extraordinary amount of searching time. In this paper we have analysed and unified the strength of techniques using structural analysis and testabilities. The new partial scan design proposed not only reduces the time for selecting scan flip-flop but also preserves high fault coverage. Test results demonstrate the high fault coverage and remarkable reduction in time for most ISCAS89 benchmark circuits.     

高频锁相环的可测性设计

边界扫描是数字电路常用的测试技术，基于IEEE1149．1标准的边界扫描技术对一款CMOS高频锁相环进行了可测性设计，该锁相环最高工作频率达GHz。详细讨论了最高输出频率、输出频率范围和锁定时间参数的测试方案，给出了详细的测试电路和测试方法。对应用该测试方案的锁相环电路增加测试电路前后的电路网表进行了Hspice仿真，仿真结果证明该方法能有效测量锁相环的参数，并且对原锁相环电路的功能影响很小。该测试方法可广泛用于高频锁相环的性能评测和生产测试。     

雷达系统软件可测试性研究

作为提高雷达软件系统可靠性的重要手段,软件可测试性一直都是该领域研究人员关注的热点和难点。文章阐述软件可测试性在现有雷达系统中的重要性、现状以及存在的不足,分析在现代雷达系统设计过程中提升软件可测试性的方法,为提高雷达系统中软件测试效率和质量提供支持。     

基于模型的综合模块化航电系统测试性设计方法

针对综合模块化航电系统对测试性提出的更高要求及其工程实践中存在的典型问题,定义了一种分布-集中式的系统测试诊断架构,以适应其体系架构的特点和生产配套关系的变化;提出了一种基于模型的系统测试性设计方法和流程,以测试性模型为驱动指导航电系统的测试性方案设计、评估与优化过程,取代传统的基于指标的测试性设计方法。在某机载综合射频系统上开展了方法应用,成功解决了该系统综合化以后测试诊断架构设计与测试性分配的非线性问题。     

TAO: regular expression-based register-transfer level testabilityanalysis and optimization

In this paper, we present testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable     

Securing Scan Control in Crypto Chips

The design of secure ICs requires fulfilling means conforming to many design rules in order to protect access to secret data. On the other hand, designers of secure chips cannot neglect the testability of their chip since high quality production testing is primordial to a good level of security. However, security requirements may be in conflict with test needs and testability improvement techniques that increase both observability and controllability. In this paper, we propose to merge security and testability requirements in a control-oriented design for security scan technique. The proposed security scan design methodology induces an adaptation of two main aspects of testability technique design: protection at protocol level and at scan path level. Without loss of generality, the proposed solution is evaluated on a simple crypto chip in terms of security and design cost.