基于软信息的CCSDS标准RS码识别算法

针对实际工程应用中的里德-所罗门(Reed-Solomon, RS)编码识别问题，根据国际空间数据系统咨询委员会(Consultative Committee for Space Data Systems, CCSDS)标准，提出了基于软信息的低复杂度缩短交织RS编码识别算法。利用码字同步算法对码字起点和缩短长度进行识别，利用接收到的RS码字计算基于校正子后验概率对数似然比平均值的编码识别特征，对码字的交织深度进行识别；进而利用识别所得的RS码交织深度和缩短长度对接收码字进行解交织和码字填充，识别RS码生成多项式。仿真结果表明，所提算法在信噪比为6.1 dB时正确识别概率即可大于90%,相较传统硬判决识别算法和基于伽罗华域快速傅里叶变换(Galois Field Fourier Transform, GFFT)的谱累积量算法均有显著的性能提升。     

在对偶基上RS码的编码和译码(英文)

本文研究采用对偶基表示域元域时Reed-Solomon码的编码和译码问题。首先介绍一般基和对偶基表示下域元素之间的转换关系,而后讨论两种表示下域元素的乘法运算。特别细致分析了普通(?)对偶(?)对偶的串行乘法器的原理和实现框图。最后详细讨论了以这种乘法器简化实现Reed-Solomon码的编、译码器的原理和框图。     

Reed-Solomon算法在RAID6系统中的应用

本文通过对纠错编码理论及有限域数学理论的研究分析,发现利用其二者相通的性质及运算规则,可以将基于Galois域的Reed-Solomon算法应用到RAID6(Redundant Array of Independent Disk 独立冗余磁盘阵列)磁盘阵列当中进行数据的恢复,并对此技术方法的性能进行了分析.     

弹载数据链系统实时RS译码器设计

为了提高传输可靠性,各种差错控制编码技术已经被广泛应用在弹载武器数据链系统中。RS( Reed-Solomon)码具有很强的抗错误能力,且码长可以灵活控制,十分适合在弹载数据链系统中应用。设计了三种不同码率的RS码,并在修正的欧几里德算法基础上进一步优化,实现了一种新型RS码实时译码器。为减少系统复杂度,该译码器复用4组基本运算单元以完成错误位置多项式和错误值多项式计算,同时也没有插入额外的流水线结构,译码过程所需的GF(28)域求逆运算则通过查找表结构实现。整个设计已经在Altera公司的EP2 S15器件上通过综合和验证,与同类设计相比占用资源大大减少,适合于高可靠性导弹数据链系统开发。     

快速响应矩阵码纠错算法的研究

在研究纠错技术的基础上，采用高级语言，实现了快速响应矩阵码中基于伽罗华域GF（28）的Reed-Solomon编码和译码算法.在编码部分提出对国际标准中生成多项式的个数进行了压缩，有效实现各版本的生成多项式：对较大版本采用交错码技术，将错误离散，提高突发错误的纠正能力.实验表明，本算法实现了高效的纠错编码和译码。     

Turbo 码编码/译码算法的FPGA实现

提出了一种用FPGA实现Turbo码编码／译码的方法,利用简单的查找表可实现经过转化后的译码算法中复杂的运算,本设计使用Altera公司的FPGA器件实现,计算机模拟表明,本设计所实现的Turbo码具有良好的性能和实用价值。     

基本电子电路

TN7022007061054基于VHDL语言的有限域正则基乘法器设计/李月乔(华北电力大学电气与电子工程学院)//电讯技术.―2006,46(6).―63～66.有限域的运算已经广泛应用于Reed-Solomon码、存储领域和各种加密算法中。乘法运算是其中最复杂的一种运算,有限域中的元素可以用各种基表示。文中在给出有限域元素自然基下的表示方法的基础上,推导出了域元素正则基下的表示方法,并给出了正则基下域元素的乘法运算,编写了乘法器的VHDL模型。用XILINX公司的ISE5.2软件对电路模型进行了仿真,结果表明乘法器的运算结果完全正确。图1表2参5TN702200706…     

环F2+uF2的Galois扩张上的迹码

环E＋uF2是介于环Z4与域F4之间的一种四元素环，因此分享了环Z4与域F4的一些好的性质，此环上的编码理论研究成为一个新的热点。该文给出了环E＋uF2的Galois扩张的相关理论，指出此Galois扩环的自同构群不同于Z4环上的Galois扩环的自同构群；定义了Galois扩环上的迹码的概念及子环子码的概念，证明了此Galois扩环上的一个码的对偶码的迹码是该环的子环子码的对偶码。     

光通信系统中基于伽罗华域乘群的QC-LDPC码的一种新颖构造方法

基于Galois域GF(q)乘群,提出了一种构造简单且编码容易实现的新颖准循环低密度奇偶校验(QC-LDPC)码构造方法,可灵活地调整码长、码率,且编译码复杂度低。用本文方法构造了适用于光通信系统的非规则QC-LDPC(3843,3603)码,仿真表明,与已广泛用于光通信系统中的经典RS(255,239)码相比,用本文方法构造的码具有更好的纠错性能,且其性能优于用SCG方法构造的LDPC码和规则的QC-LDPC(4221,3956)码,适合用于高速长距离光通信系统。     

Reed-Solomon码在MPEG-4视频流传输中的应用

本文以MPEG-4视频流作为研究的载体,详细研究基于Reed-Solomon码前向错误保护(FEC)的差错控制,实现了网络传输中的丢包恢复,并通过对算法的改进大大提高了编解码的运算速度。实验结果表明使用FEC机制可以有效提高视频传输的质量。     

An algorithm for the selection of effective error correction coding in wireless networks based on a lookup table structure

In this paper, we propose an adaptive Forward Error Correction (FEC) coding algorithm at the Medium Access Control (MAC) layer used in wireless networks. Our algorithm is based on the lookup table architecture, including a distance lookup table and a bit error rate lookup table. These tables will store the best value of the FEC codes based on different distances and bit error rates. Because radio channels change over time, the bit error rate is always changing, or in the case of mobile nodes, when the transmission distance changes, the bit error rate also changes, so previously proposed algorithms take longer to find the optimal value of the FEC code for data transmission. Our proposed algorithm, however, is based on 2 lookup tables, and thus, it can always quickly select an optimal FEC code during early data transmissions and achieve high performance. We compare our algorithm with other methods based on performance metrics such as the recovery overhead of FEC codes, energy efficiency, and peak‐signal‐to‐noise ratio values in the case of image transmission. Our simulation indicates that the proposed algorithm achieves better performances and proves the correctness of the proposed lookup table architecture.     

Concatenated coding for DS/CDMA transmission in wirelesscommunications

We investigate the use of forward-error correction (FEC) as well as concatenated coding for reliable data transmission in asynchronous direct-sequence code-division multiple-access communications over frequency-selective Rayleigh fading channels. The FEC scheme combines antenna diversity with low complexity concatenated codes which consist of a Reed-Solomon outer code and a convolutional inner code. Under this concatenated coding scheme, we analyze the average bit-error rate performance and capacity tradeoffs between various system parameters under a fixed total bandwidth expansion and concatenated codes constraint requirements     

缩短RS码的伽罗华域傅里叶变换识别方法

为了解决缩短里德-所罗门(RS)码的识别问题,提出一种基于任意长度伽罗华域傅里叶变换(GFFT)的识别方法。把限定长度GFFT拓展到任意长度,在阶数、本原多项式、码长三个维度上计算缩短RS码GFFT谱,统计谱累积量;再根据谱累积量的概率分布确定判决阈值,并进行判决,从而实现缩短RS码编码参数的识别。仿真结果表明,当阶数不大于8,误比特率不大于0.001时,采用文中识别方法可实现不小于99%的正确识别率。     

纠错编码对OCDMA系统性能的影响

提出了基于RS码(Reed-Solomon Code)的光码分多址(OCDMA)系统的前向纠错编码方案,仿真分析了该方案对一维、二维OCDMA系统的纠错能力.研究结果表明:对于相同码长、相同码重光地址码的OCDMA系统,采用前向纠错(FEC)技术能够有效降低系统误码率,提高系统客量,改善系统性能.对于来自同一码族的OCDMA系统,随码重增加,系统性能改善越好.

Abstract：

A novel forward error-correct (FEC) scheme based on Reed-Solomon code (RS code) is proposed for optical code division multiple access (OCDMA) systems.The error-correcting ability of the presented FEC scheme for one-dimension and two-dimension OCDMA systems are simulated and analyzed.Researched results show that the bit error rate (BER) of OCDMA system using FEC technology is better than that withoutwit using FEC technology at the condition of same code length and code weight.And the capacity is also largely enhanced due to the application of FEC technology.Moreover,for the address code of OCDMA system coming from the same code family,the BER is improved with the increase of the code weight.     

Selection of a forward error correcting code for the datacommunication radio link of the Advanced Train Control System

A method for selecting a forward error correcting (FEC) code for the Advanced Train Control System (ATCS) radio data link is described. The application of the ATCS and the performance issues involved in selecting a code are detailed. On the basis of the data, the ATCS Communications Component Specification Drafting Committee chose the Reed-Solomon 2 code as the FEC code for ATCS. This choice was based on best overall performance in providing throughput and good performance relative to other codes on other metrics     

A transform decoder for Reed-Solomon codes in multiple-user communication systems

Encoding and decoding algorithms for Reed-Solomon codes based on Fourier-like transforms on finite field and finite rings are discussed. Classes of codes are proposed for two different types of multiple-user communication systems: a multichannel communication system and a multiaccess communication system. For the first system, a fast decoding algorithm is developed that uses transforms on a finite ring which is isomorphic to a direct sum of Galois fields. For the second system, an efficient (in terms of information rate) coding scheme is proposed which utilizes a direct sum of Galois fields.     

RS（204,188）码连续编码的设计

先分析了RS码的编解码原理,通过MATLAB软件产生了域元素及生成多项式,还获取了RS（204,188）的编码。然后使用ISE9.2集成工具,用VERILONG语言编程,实现了连续编码。     

Design of Reed-Solomon (16,12) codec for North American AdvancedTrain Control System

The design of the codec for the ATCS radio data link is considered. The code is defined. The encoding algorithm, the decoding algorithm, and Galois field arithmetic are discussed. Implementation of the Reed-Solomon codec as a stand-alone system in order to provide a possibility of real-time bit-rate measurement is discussed. The implementation of this codec using three different 8-b and 16-b microprocessors/microcomputers is described. Their complexity and throughput are discussed     

A versatile time-domain Reed-Solomon decoder

A versatile Reed-Solomon (RS) decoder structure based on the time-domain decoding algorithm (transform decoding without transforms) is developed. The algorithm is restructured, and a method is given to decode any RS code generated by any generator polynomial. The main advantage of the decoder structure is its versatility, that is, it can be programmed to decode any Reed-Solomon code defined in Galois field (GF) 2^m with a fixed symbol size m. This decoder can correct errors and erasures for any RS code, including shortened and singly extended codes. It is shown that the decoder has a very simple structure and can be used to design high-speed single-chip VLSI decoders. As an example, a gate-array-based programmable RS decoder is implemented on a single chip. This decoder chip can decode any RS code defined in GF (2⁵) with any code word length and any number of information symbols. The decoder chip is fabricated using low-power 1.5-μ, two-layer-metal, HCMOS technology