一种用于带通Σ-Δ调制器的25MHz低功耗开关电容谐振器

介绍了一种运用于带通Σ-Δ调制器的谐振频率为25MHz的低功耗开关电容DD谐振器电路.电路采用了运算放大器共享技术和双采样技术,同时对单元电路进行优化,达到功耗最小化.该谐振器电路采用SMIC 0.25μm混合信号CMOS工艺进行设计,整个电路模块面积仅为0.09mm2.测试结果表明,使用该谐振器电路的带通Σ-Δ调制器工作于100MHz采样频率时,对于信号带宽为1kHz的输入信号,调制器的输出在谐振频率处SFDR约为77dB.整个谐振器功耗为10.5mW.     

一种超低功耗RC振荡器设计

基于SMIC 55 nm CMOS工艺,设计并制备了工作在1.2V电源电压下的超低功耗RC振荡器.该振荡器主要包括运算放大器、压控振荡器(VCO)、基准电流源、低温漂电阻和可修调开关电容以及非交叠时钟产生电路.该振荡器用工作在亚阈值区的运算放大器和VCO取代了传统单比较器型RC振荡器中的比较器,显著降低了功耗;用开关电容取代了充放电电容,并且将输出时钟的频率转换成了阻抗,与参考电阻进行比较.利用负反馈环路锁定了输出时钟信号频率,从而得到了稳定的时钟信号.测试结果表明,1.2V电源电压、27℃环境下,该RC振荡器的输出时钟信号频率为32.63 kHz,功耗为65 nW;在-10 ～ 100℃,其温度系数为1.95×10-4/℃;在0.7～1.8 V电源电压内,其电源电压调整率为3.2％/V.芯片面积为0.168 mm2.     

一种高性能、低功耗音频ΣA调制器

设计了一个应用于18位高端音频模数转换器(ADC)的三阶低功耗Σ△调制器.调制器采用2-1级联结构,通过优化调制器系数来提高其动态范围,并减小调制器输出频谱中的杂波.电路设计中采用栅源自举技术实现输入信号采样开关,有效提高了采样电路的线性度;提出一种高能效的A/AB类跨导放大器,在仅消耗0.8mA电流的情况下,达到100V/μs以上的压摆率.针对各级积分器不同的采样电容,逐级对跨导放大器进行进一步功耗优化.调制器在中芯国际0.18μm混合信号CMOS工艺中流片,芯片核心面积为1.1mm×1.0mm.测试结果表明在22.05kHz带宽内,信噪失真比和动态范围分别达到91dB和94dB.在3.3V电源电压下,调制器功耗为6.8mW,适合于高性能、低功耗音频模数转换器应用.     

一种高性能、低功耗音频ΣΔ调制器

设计了一个应用于18位高端音频模数转换器(ADC)的三阶低功耗ΣΔ调制器. 调制器采用2-1级联结构,通过优化调制器系数来提高其动态范围,并减小调制器输出频谱中的杂波. 电路设计中采用栅源自举技术实现输入信号采样开关,有效提高了采样电路的线性度;提出一种高能效的A/AB类跨导放大器,在仅消耗0.8mA电流的情况下,达到100V/μs以上的压摆率. 针对各级积分器不同的采样电容,逐级对跨导放大器进行进一步功耗优化. 调制器在中芯国际0.18μm混合信号CMOS工艺中流片,芯片核心面积为1.1mm×1.0mm. 测试结果表明在22.05kHz带宽内,信噪失真比和动态范围分别达到91dB和94dB. 在3.3V电源电压下,调制器功耗为6.8mW,适合于高性能、低功耗音频模数转换器应用.     

标准数字工艺下16位精度低压低功耗ΣΔ模数调制器设计

针对输入信号频率在20 Hz～24 kHz范围的音频应用,该文采用标准数字工艺设计了一个1.2 V电源电压16位精度的低压低功耗ΣΔ模数调制器。在6 MHz采样频率下,该调制器信噪比为102.2 dB,整个电路功耗为2.46 mW。该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器,在低电源电压情况下实现高摆率高增益要求的同时不会产生更多功耗。另外,采用高线性度、全互补MOS耗尽电容作为采样、积分电容使得整个电路可以采用标准数字工艺实现,从而提高电路的工艺兼容性、降低电路成本。与近期报道的低压低功耗ΣΔ模数调制器相比,该设计具有更高的品质因子FOM。     

CMOS图像传感器中可编程增益放大器的设计

设计了一个低功耗宽摆幅全差分开关电容可编程增益放大器(PGA).该放大器可实现近似1 dB步进,0～15 dB增益变化范围,可用于CMOS图像传感器.提出了一种可调补偿电容的运算跨导放大器(OTA),通过补偿电容调节OTA带宽,大大降低了PGA的功耗.采用TSMC 3.3 V 0.18 μm工艺,在20 MSPS采样率下,使用Hspice仿真.结果显示,电路功耗仅为7 mW,输出摆幅为轨至轨,精度为12位.     

一种欠采样应用的高精度低功耗采样/保持电路

设计了一种可用于欠采样情况的高精度、低功耗采样/保持电路。在40 MHz时钟频率下,采样90 MHz输入信号时可达11位以上精度。采用电容翻转结构的采样/保持电路,以消除电容失配的影响;使用栅压自举开关,以提高线性度,实现欠采样输入;并设计了一种高增益、大带宽、低功耗的增益自举套筒式共源共栅(telescopic cascode)运算放大器。电路采用SMIC 0.35μmCMOS工艺实现,电源电压为3.3 V,功耗仅为7.6 mW。     

一种用于自稳零放大器的伪随机信号发生器

提出了一种用于自稳零运算放大器的伪随机信号发生器电路.该电路结合了线性反馈移位寄存器和多级计数器,实现了输出信号的频率在一定范围内随机变化的功能.利用7级线性反馈移位寄存器生成的7位伪随机码对多级计数器进行置位,计数器以置位后的状态开始计数.当计数器计满时,输出信号跳变一次.同时,线性反馈移位寄存器生成新的伪随机码对计数器电路进行重新置位,计数器再重新计数.最终产生频率在一定范围内随机变化的输出信号.该输出信号作为自稳零放大器失调校准电路的开关时序信号,使自稳零运放的失调电压校准电路（开关电容结构）的开关动作具有随机化特征,产生的开关毛刺类似随机噪声,改善了自稳零放大器失调电压的校准效果.该伪随机信号发生器电路采用0.5μm CMOS工艺实现.仿真结果表明,该信号发生器电路实现产生的输出信号的频率在2 kHz到4 kHz范围内随机变化.将其用于自稳零运算放大器的失调电压校准中,自稳零运放输出信号中的谐波显著降低.     

一种用于流水线ADC采样保持电路的设计

介绍一种用于流水线ADC的采样保持电路。该电路选取电容翻转式电路结构,不仅提高整体的转换速度,而且减少因电容匹配引起的失真误差;同时使用栅压自举采样开关,有效地减少了时钟馈通和电荷注入效应;采用全差分运算放大器能有效的抑制噪声并提高整体的线性度。该采样保持电路的设计是在0.5μm CMOS工艺下实现,电源电压为5 V,采样频率为10 MHz,输入信号频率为1 MHz时,输出信号无杂散动态范围(SFDR)为73.4 dB,功耗约为20 mW。     

一种前馈架构的Σ-Δ调制器设计

基于40 nm CMOS工艺,设计了一种前馈架构的3阶1位量化离散时间Σ-Δ调制器。该调制器的信号带宽为100 kHz,过采样比为128。为了适应低电压环境,输入端开关采用栅压自举结构以提升采样信号的线性度,运算放大器采用两级结构以增加输出摆幅。为了降低系统功耗,比较器采用动态结构实现。仿真结果表明,在1.2 V电源电压下,该调制器的最高信噪比为88.1 dB,功耗为1.5 mW。     

Design of low-voltage CMOS continuous-time filter with on-chipautomatic tuning

A technique for designing a low-voltage continuous-time active filter is presented in this paper. In this technique, current sources are added to the inverting or noninverting op-amp terminals such that the op-amp input common-mode voltages can be set close to one of the supply rails to allow low-voltage operation. An automatic frequency and Q tuning technique is proposed for tuning the active filter using programmable capacitor arrays (PCAs). The proposed tuning technique does not require any peak detectors, which are difficult to implement at a low supply voltage. Instead, it uses a few analog comparators, a digital comparator, and a few binary counters to adjust the PCAs. To demonstrate the proposed techniques, a 1-V 1-MHz second-order filter fabricated in a conventional 1.2-μm CMOS process is presented. For a 5-kHz input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The frequency tuning range is between 585 kHz and 1.325 MHz. The measured power consumption for the filter alone consumes about 0.52 mW and for the entire system consumes about 1.6 mW for a supply voltage of ±0.5 V     

全差分BiCMOS采样/保持电路仿真设计

在全差分折叠式共栅-共源运放的基础上,设计了一款BiCMOS采样/保持电路。该款电路采用输入自举开关来提高线性度,同时设计的高速、高精度运放,其建立时间tS只有1.37 ns,提升了电路的速度和精度。所设计的运放中的双通道共模反馈电路使共模电压稳定输出时间tW约达1.5 ns。采用SMIC公司的0.25μmBiCMOS工艺参数,在Cadence Spectre环境下进行了仿真实验,结果表明,当输入正弦电压频率fI为10 MHz、峰-峰值UP-P为1 V,且电源电压VDD为3 V、采样频率fS为250 MHz时,所设计的采样/保持电路的无杂散动态范围SFDR约为-61 dB,信噪比SNR约为62 dB,整个电路的功耗PD约为10.85 mW,适用于10位低压、高速A/D转换器的设计。     

A 12-mW 264-MHz high linearity sharp roll-off CMOS opamp-RC low-pass filter for MB-OFDM UWB systems

This paper presents a high linearity wideband sharp roll-off Opamp-RC low-pass filter (LPF) for Ultra wideband (UWB) applications. The proposed LPF is composed of three biquads’ transfer functions with different Q-factors in series. Sharp roll-off is attributed to the steep slope of the peaking of a biquad transfer function with a high Q-factor. The superposition of these biquads also helps extend the bandwidth of the overall LPF transfer function without the cost of extra power dissipation. The effects of biquad arrangements on noise and linearity performances are investigated. A simple operational amplifier (op-amp) is adopted to ensure high frequency characteristics and high linearity performance for the designed filter. The LPF is implemented in 0.13-μm IBM CMOS process from 1.5 V supply. The measured cutoff frequency is 264 MHz with the pass-band ripple of less than 1 dB. Digital frequency tuning is implemented with 40% of tuning range around the cutoff frequency. The amount of out-of-band rejection at 290 MHz and at twice cutoff frequency is 12 dB and about 50 dB, respectively. Good linearity with IIP3 of 23 dBm is obtained. The 6th-order LPF dissipates only 12 mW with the active chip size of 400 × 640 μm².     

A CMOS highly linear channel-select filter for 3G multistandardintegrated wireless receivers

A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm² in a 0.5-μm chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54), 89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA     

Linearity performance comparison of cascode current source and single-device current source IDPs; analyses,simulations and measurements

The input differential pair (IDP) is usually a major source of nonlinear distortion in any op-amp. This is especially true if the input signal has a large common-mode component, as is the case when an op-amp functions as a unity-gain buffer or as part of a single-ended sample-hold (S/H) circuit. In this paper, we analyse the distortion of the commonly used cascode current source IDP structure and explain the sources of its nonlinear behaviour. Next, a special design technique is proposed which enhances the linearity of IDPs. The circuit uses a single device current source that has the same channel length while its width is double those of IDP devices. Theoretical analysis, as well as simulation and experimental results, is given to confirm the improved linearity of a unity gain buffer. Simulations predict improvements up to 20 dB. 15 dB total harmonic distortion (THD) reduction was also achieved for a 15 MHz input signal based on measurement of a test chip. The method is valuable as power supply voltages shrink, and the design offers extra voltage headroom at input.     

Least mean square adaptive digital background calibration of pipelined analog-to-digital converters

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.     

基于动态栅压功放的高效超宽带发射机结构

提出的超宽带射频发射机的结构具有良好的效率和线性度。设计和制作了一款宽带的动态栅压偏 置的功率放大器。动态栅压偏置可以获得优良的宽带性能。总发射机可以支持184.32 MHz 的调制带宽。基带信 号和相关偏置电压由宽带模拟基带处理单元生成。基带信号经过直接变频的调制方式到达功放输入端,偏置电压 经过差分运放以及延时电路到达功放栅极。实验结果表明,与传统A 类功放相比,动态栅压偏置可以增加系统的效 率和线性度。     

运放单电源放大电路设计方法

对称供电的运放在交流应用时可改用单电源工作,但改变供电方式也带来偏置,带宽,稳定性等问题.通过对同相、反相两种输入方式电路的分析和计算,给出了单电源运放电路的设计和评价方法.     

一种高线性Gm-C复数滤波器的设计

针对低电源电压Gm-C复数滤波器线性度不足的问题,提出了一种使用大信号线性化技术的一阶复数带通滤波器。所提出的复数滤波器使用了不平衡差分对和自适应偏置电路两种线性化技术,通过扩展跨导相对恒定的输入电压范围提高滤波器的线性度。滤波器采用UMC 110 nm CMOS工艺设计,中心频率和带宽分别为2 MHz和1 MHz。Cadence仿真结果显示,在1.2 V电源电压下,滤波器功耗为229μW,镜像抑制比(IIR)为18 dB,线性度(输入三阶交调点IIP3)为9.53 dBm,总谐波失真(THD)为-55.7 dB。该复数滤波器电路结构简单、功耗较低,以期能广泛应用于低电源电压的接收机设计。     

低电压、高速、高稳定性集成运算放大器芯片设计

基于0.18μmCMOS标准工艺,设计了一种工作电压为1.8V、带宽达到910MHz的高速、宽带、高稳定性的集成运算放大器芯片。阐述了该放大器电路构成原理、弥勒补偿电容和调零电阻补偿的应用方法、集成三支路基准电流源与低压共源共栅偏置电流分配电路的设计方法。利用CadenceSpectre仿真器对芯片版图进行了后端仿真验证测试。通过对测试结果的分析,表明了本设计能够有效提高系统的稳定性和速度,并具有优良电源抑制比和较大的输出摆幅。最后给出了芯片设计达到的结果。仿真测试结果表明,本设计芯片可应用于中频段需要对微弱信号处理的放大、模拟运算、有源滤波、AGC等电子系统。