A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems

In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18- $mu{hbox{m}}$ technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5% less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4%. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.      

Effective Timing Error Tolerance in Flip-Flop Based Core Designs

Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs are introduced, which exploit a transition detector for timing error detection along with asynchronous local error correction schemes to provide timing error tolerance. The proposed, the Razor and the Time Dilation techniques were applied separately in the design of three versions of a 32-bit MIPS microprocessor core and the pci_bridge32 IWLS05 core, using a 90 nm CMOS technology. Comparisons based on simulation results validate the efficiency of the new design approach.     

An on-chip ECC circuit for correcting soft errors in DRAMs withtrench capacitors

A modified error-correcting code that can correct up to two soft errors on each row (word line) in a dynamic random-access memory (DRAM) chip is proposed. Double-bit soft errors frequently occur in DRAM cells with trench capacitors, when charged alpha particles impinge on the intervening space between two vertical capacitors causing plasma shorts between them. The conventional on-chip error-correcting codes (ECCs) cannot correct such double-bit word-line soft errors, which significantly increase the uncorrectable error rate (UER). An ECC circuit that uses an augmented rectangular product code to detect and correct double-bit soft errors is presented. The proposed circuit automatically corrects the addressed bit if it is faulty, and then quickly locates the other faulty bit. A comprehensive study is made to estimate improvements in soft error rate (SER) and mean time to failure (MTTF). The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed by combinatorial enumeration     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs

Registers are one of the circuit elements that can be affected by soft errors. To ensure that soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is commonly used to protect registers. TMR can effectively protect against errors affecting a single flip-flop and has a low overhead in terms of circuit delay. The main drawback of TMR is that it requires more than three times the original circuit area as the flip-flops are triplicated and additional voting logic is inserted. Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations. In this paper, DMR + an alternative to TMR to protect registers in FPGAs, is presented. The proposed scheme exploits the FPGA structure to achieve a reduction in the FPGA resources (LUTs and Flip-Flops) at the cost of a certain overhead in delay. DMR + can correct all single bit errors like TMR but is more vulnerable to multiple bit errors. To evaluate the benefits, the DMR + technique has been implemented and compared with TMR considering standalone registers and also some simple designs.     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

A Stage-Wise Soft-Error Detection Scheme for Flip-Flop Based Pipelines in Secure Cloud Servers

The shrinking feature sizes make transistors increasingly susceptible to soft errors, which can severely degrade the systems’ RAS (Reliability, Availability, and Serviceability). The tough challenge results from not only increasing SER (soft error rate) of storage cells, but also the increasing susceptibility of combinational logics to soft errors. How to efficiently detect soft errors becomes the primary problem in the Backward Error Recovery (BER) schemes that are cost-effective in soft error tolerance. This paper presents a soft error detection scheme, AUDITOR, for flip-flop based pipelines. The AUDITOR copes with both types of soft errors—single event upset (SEU) and single event transient (SET). We propose a “local-audit” fault detection mechanism, by which each pipeline stage is verified independently and the verifying result registers with a dedicated “audit” bit (V-bit). All the V-bits are distributed across the whole pipeline and synergically monitor the pipeline execution. To relax the constraint of SET detection capability imposed by the inherent fully synchronous operation mode in flip-flop based pipelines, we firstly propose using path-compensation technique to address this constraint. Furthermore, a reuse-based design paradigm is employed to reduce the implementation complexity and area overhead. The AUDITOR possesses robust detection capability and short detection latency, at the expense of about 29 % and 50 % increase in area and power consumption, respectively.     

A comparison of fault-tolerant state machine architectures forspace-borne electronics

Very large scale integrated (VLSI) circuits used in the space and nuclear industry are continuously subjected to ion radiation. As the limits of VLSI technology are pushed towards sub-micron levels in order to achieve higher levels of integration, devices become more vulnerable to radiation induced errors. These radiation induced errors can lead to system failure, particularly if they affect the memory portion of vital subsystems, such as state machine controllers. This paper explores the use of classical fault-tolerant state machine architectures based on hardware and information redundancy to design radiation-immune controllers. Those architectures particularly suitable for VLSI-implementation using ordinary low power CMOS technology are identified, with the primary objective of correcting single flip-flop errors. Each architecture was implemented on a set of benchmark sequential circuits and evaluated in terms of circuit-size and maximum path-delay. The best overall architectures, `SEU-I TMR' and `Modified Explicit EC', used a nonredundant excitation circuit and redundant flip-flops, followed by error correction circuitry to tolerate single flip-flop errors     

Level conversion for dual-supply systems

Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Additionally, circuit robustness against supply bounce is a key property that differentiates good level converter design. Novel flip-flops presented in this paper incorporate a half-latch level converter and a precharged level converter. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip-flop. These benefits are accompanied by 24% flip-flop robustness improvement leading to 13% delay spread reduction in a CVS critical path. The proposed flip-flops also show 18% layout area reduction. Advantages of level conversion in a flip-flop over asynchronous level conversion in combinational logic are also discussed in terms of delay penalty and its sensitivity to supply bounce.     

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively     

Switch-level soft error emulation for SET-induced pulses of variable strengths

Due to the increased complexity of modern digital circuits, the use of simulation-based soft error detection methods has become cumbersome and very time-consuming. FPGA-based emulation provides an attractive alternative, as it can not only provide faster speed, but also handle highly complex circuits. In this work, a novel FPGA-based soft error detection technique is proposed, which enables detection of soft errors resulting from voltage pulses of different magnitudes induced by single-event transients (SETs). The paper analyzes the effect of transient injection location on soft error rate (SER) and applies the idea of transient equivalence to minimize resource overhead as well as speed-up emulation process. Switch-level implementations of ISCAS’85 benchmarks are designed using gate-level structures and experimental results are reported. The results show that an application of transient equivalence results in an emulation speed-up of 2.875 and reduces the memory utilization by 65%. An average soft error rate (SER) of 0.7-0.8 was achieved using the proposed strength-based detection with drain as transient injection location, showing that voltage pulses of magnitude smaller than logic threshold can eventually result in soft errors. Furthermore, the presented emulation-based soft error detection technique achieved significant speed-up of the order of 10⁶ compared to a customized simulation-based method.     

Error probability minimizing pilots for OFDM with M-PSK modulation over Rayleigh-fading channels

Orthogonal frequency division multiplexing (OFDM) with pilot symbol assisted channel estimation is a promising technique for high rate transmissions over wireless frequency-selective fading channels. In this paper, we analyze the symbol error rate (SER) performance of OFDM with M-ary phase-shift keying (M-PSK) modulation over Rayleigh-fading channels, in the presence of channel estimation errors. Both least-squares error (LSE) and minimum mean-square error (MMSE) channel estimators are considered. For prescribed power, our analysis not only yields exact SER formulas, but also quantifies the performance loss due to channel estimation errors. We also optimize the number of pilot symbols, the placement of pilot symbols, and the power allocation between pilot and information symbols, to minimize this loss, and thereby minimize SER. Simulations corroborate our SER performance analysis, and numerical results are presented to illustrate our optimal claims.     

Low clock-swing conditional-precharge flip-flop for more than 30%power reduction

A low clock-swing flip-flop based on a conditional precharge scheme is proposed to save both clock system power and supply power. Unlike previous reduced clock-swing flip-flops, the new flip-flop will not precharge and discharge when the input data do not change. Compared with previous low clock-swing flip-flops, the new flip-flop leads to savings of at least 30% of the total power     

Loosely coupled multi-bit flip-flop allocation for power reduction

Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. In this work, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart (i.e., no relocation), providing no need to set aside white space. Utilizing LC-MBFFs, we propose a multi-bit flip-flop allocation algorithm which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that our proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power by 8.51% while the best known multi-bit flip-flop allocation algorithm [7] reduces by 5.37%. Additionally, we extend our algorithm to support the multi-bit flip-flop allocation for circuits with clock polarity assignment.     

Low power double edge-triggered flip-flop using one latch

A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit data are sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops     

新型半静态低功耗D触发器设计

本文从简化触发器内部锁存器结构以降低功耗的要求出发，提出了一种新型的半静态D触发器设计。PSPICE模拟表明，新设计逻辑功能正确。与以往一些设计相比，新设计在功耗和速度上获得显著改进。     

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree

The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.     

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in the state-holding latch node. The RazorII flip-flop naturally detects logic and register SER. We implement a 64-bit processor in 0.13 mum technology which uses RazorII for SER tolerance and dynamic supply adaptation. RazorII based DVS allows elimination of safety margins and operation at the point of first failure of the processor. We tested and measured 32 different dies and obtained 33% energy savings over traditional DVS using RazorII for supply voltage control. We demonstrate SER tolerance on the RazorII processor through radiation experiments.     

Low power flip-flop with clock gating on master and slave latches

A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity