Novel low power reversible binary incrementer design using quantum-dot cellular automata

This paper demonstrates the design of n-bit novel low power reversible binary incrementer in Quantum-Dot Cellular Automata (QCA). The comparison of quantum cost in quantum gate based approach and in QCA based design agreed the cost efficient implementation in QCA. The power dissipation by proposed circuit is estimated, which shows that the circuit dissipates very low heat energy suitable for reversible computing. All the circuits are evaluated in terms of logic gates, circuit density and latency that confirm the faster operating speed at nano scale. The reliability of the circuit under thermal randomness is explored which describes the efficiency of the circuit.     

Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication

Quantum-dot cellular automata (QCA) is an emerging area of research in reversible computing. It can be used to design nanoscale circuits. In nanocommunication, the detection and correction of errors in a received message is a major factor. Besides, device density and power dissipation are the key issues in the nanocommunication architecture. For the first time, QCA-based designs of the reversible low-power odd parity generator and odd parity checker using the Feynman gate have been achieved in this study. Using the proposed parity generator and parity checker circuit, a nanocommunication architecture is proposed. The detection of errors in the received message during transmission is also explored. The proposed QCA Feynman gate outshines the existing ones in terms of area, cell count, and delay. The quantum costs of the proposed conventional reversible circuits and their QCA layouts are calculated and compared, which establishes that the proposed QCA circuits have very low quantum cost compared to conventional designs. The energy dissipation by the layouts is estimated, which ensures the possibility of QCA nano-device serving as an alternative platform for the implementation of reversible circuits. The stability of the proposed circuits under thermal randomness is analyzed, showing the operational efficiency of the circuits. The simulation results of the proposed design are tested with theoretical values, showing the accuracy of the circuits. The proposed circuits can be used to design more complex low-power nanoscale lossless nanocommunication architecture such as nano-transmitters and nano-receivers.     

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

Novel designs of nanometric parity preserving reversible compressor

Reversible logic is a new field of study that has applications in optical information processing, low power CMOS design, DNA computing, bioinformatics, and nanotechnology. Low power consumption is a basic issue in VLSI circuits today. To prevent the distribution of errors in the quantum circuit, the reversible logic gates must be converted into fault-tolerant quantum operations. Parity preserving is used to realize fault tolerant in this circuits. This paper proposes a new parity preserving reversible gate. We named it NPPG gate. The most significant aspect of the NPPG gate is that it can be used to produce parity preserving reversible full adder circuit. The proposed parity preserving reversible full adder using NPPG gate is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. Compressors are of importance in VLSI and digital signal processing applications. Effective VLSI compressors reduce the impact of carry propagation of arithmetic operations. They are built from the full adder blocks. We also proposed three new approaches of parity preservation reversible 4:2 compressor circuits. The third design is better than the previous two in terms of evaluation parameters. The important contributions have been made in the literature toward the design of reversible 4:2 compressor circuits; however, there are not efforts toward the design of parity preservation reversible 4:2 compressor circuits. All the scales are in the nanometric criteria.     

Design of dual-edge triggered flip-flops based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has been widely considered as an alternative to complementary metal-oxide-semiconductor (CMOS) due to QCA’s inherent merits.Many interesting QCA-based logic circuits with smaller feature size,higher operating frequency,and lower power consumption than CMOS have been presented.However,QCA is limited in its sequential circuit design with high performance flip-flops.Based on a brief introduction of QCA and dual-edge triggered (DET) flip-flop,we propose two original QCA-based D and JK DET flip-flops,offering the same data throughput of corresponding single-edge triggered (SET) flip-flops at half the clock pulse frequency.The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool.All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput.Furthermore,compared with a previous DET D flip-flop,the number of cells,covered area,and time delay of the proposed DET D flip-flop are reduced by 20.5%,23.5%,and 25%,respectively.By using a lower clock pulse frequency,the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high performance.     

On figures of merit in reversible and quantum logic designs

Five figures of merit including number of gates, quantum cost, number of constant inputs, number of garbage outputs, and delay are used casually in the literature to compare the performance of different reversible or quantum logic circuits. In this paper we propose new definitions and enhancements, and identify similarities between these figures of merit. We evaluate these measures to show their strength and weakness. Instead of the number of gates, we introduce the weighted number of gates, where a weighting factor is assigned to each quantum or reversible gate, based on its type, size and technology. We compare the quantum cost with weighted number of gates of a circuit and show three major differences between these measures. It is proved that it is not possible to define a universal reversible logic gate without adding constant inputs. We prove that there is an optimum value for number of constant inputs to obtain a circuit with minimum quantum cost. Some reversible logic benchmarks have been synthesized using Toffoli and Fredkin gates to obtain their optimum values of number of constant inputs. We show that the garbage outputs can also be used to decrease the quantum cost of the circuit. A new definition of delay in quantum and reversible logic circuits is proposed for music line style representation. We also propose a procedure to calculate the delay of a circuit, based on the quantum cost and the depth of the circuit. The results of this research show that to achieve a fair comparison among designs, figures of merit should be considered more thoroughly.      

Design and analysis of area efficient QCA based reversible logic gates

The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

Multi-objective optimization of QCA circuits with multiple outputs using genetic programming

Quantum-Dot Cellular Automata (QCA) is a promising nanotechnology that has been recognized as one of the top emerging technologies in future computers. Size density of several orders of magnitude smaller than Complementary Metal-Oxide Semiconductor, fast switching time and extremely low power, has caused QCA to become a topic of intense research. The majority gate and the inverter gate together make a universal set of Boolean primitives in QCA technology. Reducing the number of required primitives to implement a given Boolean function is an important step in designing QCA logic circuits. Previous research has shown how to use genetic programming to minimize the number of gates implementing a given Boolean function with one output. In this paper, we first show how to minimize the gates for the given Boolean truth tables with an arbitrary number of outputs using genetic programming. Then, another criterion, reduction of the delay of the implementing circuit is considered. Multi-objective genetic programming is applied to simultaneously optimize both objectives. The results demonstrate the proposed approach is promising and worthy of further research.     

Towards ultra-efficient QCA reversible circuits

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.     

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.     

Controlled gates for multi-level quantum computation

Multi-level (ML) quantum logic can potentially reduce the number of inputs/outputs or quantum cells in a quantum circuit which is a limitation in current quantum technology. In this paper we propose theorems about ML-quantum and reversible logic circuits. New efficient implementations for some basic controlled ML-quantum logic gates, such as three-qudit controlled NOT, Cycle, and Self Shift gates are proposed. We also propose lemmas about r-level quantum arrays and the number of required gates for an arbitrary n-qudit ML gate. An equivalent definition of quantum cost (QC) of binary quantum gates for ML-quantum gates is introduced and QC of controlled quantum gates is calculated.     

Toward novel designs of reversible ternary 6:2 Compressor using efficient reversible ternary full-adders

Integrated circuits always face with two major challenges including heat caused by energy losses and the area occupied. In recent years, different strategies have been presented to reduce these two major challenges. The implementations of circuits in a reversible manner as well as the use of multiple-valued logic are among the most successful strategies. Reversible circuits reduce energy loss and ultimately eliminate the problem of overheating in circuits. Preferring multiple-valued logic over binary logic can also greatly reduce area occupied of circuits. When switching from binary logic to multiple-valued logic, the dominant thought in binary logic is the basis of designing computational circuits in multiple-valued logic, and disregards the capabilities of multiple-valued logic. This can cause a minimal use of multiple-valued logic capabilities, increase complexity and delay in the multiple-valued computational circuits. In this paper, we first introduce an efficient reversible ternary half-adder. Afterward, using the reversible ternary half-adder, we introduce two reversible versions of traditional and comprehensive reversible ternary full-adders. Finally, using the introduced reversible ternary full-adders, we propose two novel designs of reversible ternary 6:2 Compressor. The results of the comparisons show that although the proposed circuits are similar to or better than previous corresponding designs in terms of criteria number of constant input and number of garbage outputs, they are superior in criterion quantum cost.

     

High performance nanocomparator: a quantum dot cellular automata-based approach

Quantum dot cellular automata (QCA) are emerging nanotechnology that offers few significant advantages like faster speed, higher circuit density, and lower power dissipation. Comparator is a fundamental and essential block in QCA logic circuit family. In this article, a single-layered and straightforward design of a QCA-based one-bit magnitude comparator has been proposed. The proposed design is 6.38%, 6.67% and?~?10% more efficient in cell complexity, cell area and total area measurement, respectively, in comparison to prior reported designs. Furthermore, the energy dissipation of the proposed circuit has been calculated using QCADesigner-E and QCAPro tools to check the energy efficiency of the proposed circuit. The total energy dissipation of the reported magnitude comparator is 19.50 meV when measured using the QCADesigner-E tool. Similarly, according to the QCAPro tool, it has?~?71% less energy dissipation than the existing designs.

     

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.     

Novel parity-preserving reversible logic array multipliers

Reversible logic as a new promising design domain can be used for DNA computations, nanocomputing, and especially constructing quantum computers. However, the vulnerability to different external effects may lead to deviation from producing correct results. The multiplication is one of the most important operations because of its huge usage in different computing systems. Thus, in this paper, some novel reversible logic array multipliers are proposed with error detection capability through the usage of parity-preserving gates. By utilizing the new arrangements of existing reversible gates, some new circuits are presented for partial product generation and multi-operand addition required in array multipliers which results in two unsigned and three signed parity-preserving array multipliers. The experimental results show that the best of signed and unsigned proposed multipliers have the lowest values among the existing designs regarding the main reversible logic criteria including quantum cost, gate count, constant inputs, and garbage outputs. For \(4\times 4\) multipliers, the proposed designs achieve up to 28 and 46% reduction in the quantum cost and gate count, respectively, compared to the existing designs. Moreover, the proposed unsigned multipliers can reach up to 58% gate count reduction in \(16\times 16\) multipliers.     

Implementing a one-bit reversible full adder using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technique is one of the emerging and promising nanotechnologies. It has considerable advantages versus CMOS technology in various aspects such as extremely low power dissipation, high operating frequency and small size. In this paper, designing of a one-bit full adder is investigated using a QCA implementation of Toffoli and Fredkin gates. Then, a full adder design with reversible QCA1 gates is proposed regarding to overhead and power savings. Our proposed full adder design is more preferable when considering both circuit area and speed. The proposed design uses only two QCA1 gates and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells.     

A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry

Multiple-valued quantum logic circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum logic circuits. Adder/subtractor is the major component of the ALU of a computer and is also used in quantum oracles. In this paper, we propose a recursive method of hand synthesis of reversible quaternary full-adder circuit using macro-level quaternary controlled gates built on the top of ion-trap realizable 1-qudit quantum gates and 2-qudit Muthukrishnan–Stroud quantum gates. Based on this quaternary full-adder circuit we propose a reversible circuit realizing quaternary parallel adder/subtractor with look-ahead carry. We also show the way of adapting the quaternary parallel adder/subtractor circuit to an encoded binary parallel adder/subtractor circuit by grouping two qubits together into quaternary qudit values.     

Design of BCD adder with five input majority gate for QCA

In the digital world BCD numbers play a pivotal role in constituting decimal numbers. New different technologies are emerging in order to obtain low area/power/delay factors to replace the CMOS technology. One such technology is quantum cellular automata (QCA) realization, through which many arithmetic circuits can be designed. This paper deals with the implementation of BCD adder with 5 input majority gates for QCA. The 3 input majority gate and an inverter are basic elements of QCA. In this project amalgamation of majority gates with 3 and 5 inputs are used instead of implementing the entire circuit using 3 input majority gate in the BCD i.e. mainly comprised by partly consumed gates and entirely consumed gates. The proposed is designed and functional verification is done by Verilog HDL and Modelsim version 10.4a. The proposed design has been verified and the delay of existing and proposed design is analysed using Xilinx tool. The numbers of partly consumed and entirely consumed gates are less when compared to the existing method of implementation. The delay is reduced compared to the existing system which shows the improvement of 9.84%. The drawback of crossovers that leads the difficulty in implementation and reduces the efficiency of the circuit is reduced in the proposed implementation.     

量子逻辑电路中控制点失效错误的定位

确保可逆电路的正确性与可靠性,错误检测必不可少,错误定位难度更高.通过分析发现当可逆电路中规模为k的可逆门发生控制点失效时仅对2<'n-k>个输入向量的输出产生影响,据此给出了一种把当前错误集分成若干个子集的方法生成控制点失效错误定位树.传统的错误定位方法都是通过生成真值表和错误表来产生错误定位树;该方法不需要生成和存储真值表以及错误表就能够有效定位电路中控制点失效错误.与Rfault算法相比,空间复杂度和时间复杂度更小,算法效率更高,能应用于更大规模的电路.