Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.     

Single electron transistor with P-type sidewall spacer gates

A single-electron transistor (SET) is one of the promising solutions to overcome the scaling limit of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Up to now, various kinds of SETs are being proposed and SETs with a dual gate (DG) structure using an electrical potential barrier have been demonstrated for room temperature operation. To operate DG-SETs, however, extra bias of side gates is necessary. It causes new problems that the electrode for side gates and the extra bias for electrical barrier increase the complexity in circuit design and operation power consumption, respectively. For the reason, a new mechanism using work function (WF) difference is applied to operate a SET at room temperature by three electrodes. Its structure consists of an undoped active region, a control gate, n-doped source/drain electrodes, and metal/silicide or p-type silicon side gates, and a SET with metal/silicide gates or p-type silicon gates forms tunnel barriers induced by work function between an undoped channel and grounded side gates. Via simulation, the effectiveness of the new mechanism is confirmed through various silicide materials that have different WF values. Furthermore, by considering the realistic conditions of the fabrication process, SET with p-type sidewall spacer gates was designed, and its brief fabrication process was introduced. The characteristics of its electrical barrier and the controllability of its control gate were also confirmed via simulation. Finally, a single-hole transistor with n-type sidewall spacer gates was designed.     

3-D Design and Analysis of Functional NEMS-gate MOSFETs and SETs

Nanoelectromechanical system (NEMS)-gate metal- oxide-semiconductor field effect transistor (MOSFET) and single- electron transistor (SET) structures are investigated by combining 3-D design and SPICE simulation. First, the metal gate is simulated by using a 3-D simulator, which enables to design realistic 3-D device structures, and its movement is studied for different design parameters. It is demonstrated that a low stiffness design of the structure is essential for a low-voltage actuation. Results are compared with theoretical numerical simulation and a tunable capacitor model is then embedded in a SPICE simulator and coupled either with a transistor model for MOS-NEMS or with a newly developed SET analytical model for SET-NEMS. It is shown that the use of NEMS membrane can add new functionalities to conventional MOSFET and SET, such as very abrupt switching of the current, which can break theoretical limits of MOSFET, or modulation of Coulomb oscillations governing SET characteristics     

Advances in the modeling of single electron transistors for the design of integrated circuit

Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy.     

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels

A compact and analytical model for silicon single-electron transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is proposed. The model is based on a steady-state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of electrons in the dot to reduce the complexity while accounting for the quantum-level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance (NDC) characteristics and aperiodic Coulomb oscillations due to nonuniform quantum-level spacings can be reproduced in this model. The model was compared with measurements, and good agreement was obtained. Simulations of some basic circuits that utilize NDC are successfully carried out by applying our model to the HSPICE circuit simulation. Our model can provide suitable environments for designing CMOS-combined room-temperature-operating highly functional SET circuits.     

Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier

As a solution to the high speed, ultralow power, and extremely compact ADC circuit block, a complementary single-electron transistor (SET)/CMOS hybrid amplifier-based analog-to-digital converter (ADC) is proposed. It is implemented with a physics-based SPICE model including nonideal effects in real Si-based SET_s such as the tunnel barrier lowering effect, parasitic MOSFET_s operation, and the phase shift of Coulomb oscillation by the bias of a gate other than a main control gate. Its core scheme is the combination of both the amplification of SET current by MOSFET_s and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In addition, the transient operation of SET/CMOS hybrid circuit-based ADC_s fully accounting for nonideal effects of real SET_s is successfully demonstrated for the first time. Compared with the previous SET-based ADC_s, our ADC makes features of the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability.     

Impact of Key Circuit Parameters on Signal-to-Noise Ratio Characteristics for the Radio Frequency Single-Electron Transistors

Hybrid simulation was performed to analyze the response of the real-time reflection-type radio frequency single-electron transistor (RF-SET) measurement system. A compact and physically-based analytical SET model, which was validated with a Monte Carlo simulator, was used to simulate the SET characteristics, while SPICE equivalent circuits were implemented to simulate all other components of the RF-SET measurement system. The impact of various key parameters on the RF-SET response was demonstrated for a carrier frequency much less than I/e ( is the typical current through the SET). It was revealed that an inevitable feed-through loss between the tank circuit and the cryogenic amplifier, and high-frequency parasitics of the inductor degrade the RF-SET performance significantly. As such, they have to be optimized to experimentally realize the shot-noise-limited charge sensitivity.     

Binary adders of multigate single-electron transistors: specific design using pass-transistor logic

We describe how to construct area-efficient adders using single-electron transistors (SETs). The design is based on pass-transistor logic and multigate SETs are used as pass transistors. The proposed design enables us to construct a full adder using only six SETs. We also show that multibit binary adders can be built using cascaded SET structures without any long wires. The small number of transistors and no-metal-interconnection configuration significantly reduces the circuit area and capacitance to be charged. A Monte Carlo simulation shows that even when the inter-SET-node capacitances are reduced and consequently the carry signal level terribly fluctuates in its path due to single-electron charging effects, the carry can correctly propagate as long as the final output node capacitance is sufficiently large. This proves that the area reduction and speed improvement are compatible in our design. We also discuss the possibility of large-scale integration, touching on the random-offset-charge issue.     

Single-electron transistors based on gate-induced Si island for single-electron logic application

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated.     

A SPICE-Compatible New Silicon Nanowire Field-Effect Transistors (SNWFETs) Model

Extraction of carrier mobilities of silicon nanowire FETs (SNWFETs) with Schottky source and drain contacts is performed using a newly developed compact model, which is suitable for efficient circuit simulation. The SNWFET model is based on an equivalent circuit including a Schottky diode model for two metal-semiconductor contacts and a SPICE LEVEL 3 MOSFET model for an intrinsic NW. The Schottky diode model is based on our recently developed Schottky diode model that includes thermionic field emission for reverse bias and thermionic emission mechanism for forward bias. It also includes a new analytical Schottky barrier height model dependent on the gate voltages as well as the drain-source voltages. The results simulated from the SNWFET model reproduce various, previously reported experimental results within 10% errors. The mobilities extracted from our model are compared with the mobility calculated without considering the Schottky contacts.     

High-Precision Displacement Sensing of Monolithic Piezoelectric Disk Resonators Using a Single-Electron Transistor

A single-electron transistor (SET) can be used as an extremely sensitive charge detector. Mechanical displacements can be converted into charge, and hence, SETs can become sensitive detectors of mechanical oscillations. For studying small-energy oscillations, an important approach to realize the mechanical resonators is to use piezoelectric materials. Besides coupling to traditional electric circuitry, the strain-generated piezoelectric charge allows for measuring ultrasmall oscillations via SET detection. Here, we explore the usage of SETs to detect the shear-mode oscillations of a 6-mm-diameter quartz disk resonator with a resonance frequency around 9 MHz. We measure the mechanical oscillations using either a conventional DC SET, or use the SET as a homodyne or heterodyne mixer, or finally, as a radio-frequency single-electron transistor (RF-SET). The RF-SET readout is shown to be the most sensitive method, allowing us to measure mechanical displacement amplitudes below \(10^{-13}\) m. We conclude that a detection based on a SET offers a potential to reach the sensitivity at the quantum limit of the mechanical vibrations.     

Effects of oxidation process on the tunneling barrier structures in room-temperature operating silicon single-electron transistors

We investigate the tunneling barrier structures in the room-temperature operating silicon single-electron transistors (SETs). The devices are fabricated in the form of the point-contact channel metal-oxide-semiconductor field-effect transistors with gate oxide formed by thermal oxidation or low-pressure chemical vapor deposition (LP-CVD). From the gate voltage and temperature dependence of the peak current in the SET characteristics, it is found that the thermal oxidation process leads to higher and narrower tunneling barriers. In some SETs with CVD-deposited gate oxide, thermally activated conduction over the low tunneling barriers is clearly observed in a wide temperature range from 100 K-300 K.     

Large Coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFETs formed by slight oxidation process

We propose a new fabrication technique of room-temperature operating silicon single-electron transistors (SETs). The devices are in the form of ultranarrow wire channel MOSFETs, where a sub-10-nm channel is formed by wet etching and slight thermal oxidation. Large Coulomb blockade (CB) oscillations whose peak-to-valley current ratio at room temperature is as high as 6.8 are observed in the fabricated ultranarrow wire channel MOSFETs. It is found that larger CB oscillations are obtained in the ultranarrow wire channel SETs than in the point-contact channel SETs. It is considered that the potential fluctuations induced during the channel formation processes give rise to multiple-dot SET structures in the ultranarrow wire channel MOSFETs.     

A two-step methodology for CMOS VLSI reliability improvement: Step one

Reliability improvement of CMOS VLSI circuits depends on a thorough understanding of the technology, failure mechanisms, and resulting failure modes involved. Failure analysis has identified open circuits, short circuits and MOSFET degradations as the prominent failure modes. Classical methods of fault simulation and test generation are based on the gate level stuck-at fault model. This model has proved inadequate to model all realistic CMOS failure modes. An approach, which will complement available VLSI design packages, to aid reliability improvement and assurance of CMOS VLSI is outlined. A ‘two-step’ methodology is adopted. Step one, described in this paper, involves accurate circuit level fault simulation of CMOS cells used in a hierarchical design process. The simulation is achieved using SPICE and pre-SPICE insertion of faults (PSIF). PSIF is an additional module to SPICE that has been developed and is outlined in detail. Failure modes effects analysis (FMEA) is executed on the SPICE results and FMEA tables are generated. The second step of the methodology uses the FMEA tables to produce a knowledge base. Step two is essential when reliability studies of larger and VLSI circuits are required and will be the subject of a future paper. The knowledge base has the potential to generate fault trees, fault simulate and fault diagnose automatically.     

Realization of multiple valued logic and memory by hybrid SETMOS architecture

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.     

Accurate and computer efficient modelling of single event transients in CMOS circuits

A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate     

Bias spectroscopy and simultaneous single-electron transistor charge state detection of Si:P double dots

We report a detailed study of low-temperature (mK) transport properties of a silicon double-dot system fabricated by phosphorous ion implantation. The device under study consists of two phosphorous nanoscale islands doped to above the metal-insulator transition, separated from each other and the source and drain reservoirs by nominally undoped (intrinsic) silicon tunnel barriers. Metallic control gates, together with an Al-AlO(x) single-electron transistor (SET), were positioned on the substrate surface, capacitively coupled to the buried dots. The individual double-dot charge states were probed using source-drain bias spectroscopy combined with non-invasive SET charge sensing. The system was measured in linear (source-drain DC bias V(SD) = 0) and non-linear (V(SD) ≠ 0) regimes, allowing calculations of the relevant capacitances. Simultaneous detection using both SET sensing and source-drain current measurements was demonstrated, providing a valuable combination for the analysis of the system. Evolution of the triple points with applied bias was observed using both charge and current sensing. Coulomb diamonds, showing the interplay between the Coulomb charging effects of the two dots, were measured using simultaneous detection and compared with numerical simulations.     

Three-dimensional simulation of realistic single electron transistors

We present an approach, and its implementation in a computer program, for the three-dimensional (3-D) simulation of realistic single electron transistor (SET) structures, in which subregions with different degrees of quantum confinement are simultaneously considered. The proposed approach is based on the self-consistent solution of the many body Schrodinger equation with density functional theory and on the computation of the conductance of tunnel constrictions through the solution of the 3-D Schrodinger equation with open boundary conditions. We have developed an efficient code (ViDES) based on such an approach. As examples of addressable SET structures, we present the simulation of a SET, one defined by metal gates on an AlGaAs/GaAs heterostructures, and of a SET defined by etching and oxidation on the silicon-on-insulator material system. Since SETs represent prototypical nanoscale devices, the code may be a valuable tool for the investigation and optimization of a broad range of nanoelectronic solid-state devices.     

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “ quantization threshold”) that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studied for the current-biased negative differential resistance (NDR) circuit and hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.