蓝牙收发器中的CMOS低噪声放大器的设计与测试

介绍了一种基于 0 35 μmCMOS数字工艺、集成于单片蓝牙收发器中的射频低噪声放大器 .在考虑ESD保护和封装的情况下 ,从噪声优化、阻抗匹配及增益的角度讨论了电路的设计方法 .经测试 ,在 2 0 5GHz的中心频率处 ,S11为 - 6 4dB ,S2 1为 11dB ,3dB带宽约为 30 0MHz,噪声系数为 5 3dB .该结果表明 ,射频电路设计需要全面考虑寄生效应 ,需要合适的封装模型以及合理的工艺     

低压中和化CMOS差分低噪声放大器设计

以设计低电压LNA电路为目的,提出了一种采用关态MOSFET中和共源放大器输入级栅漏寄生电容Cgd的CMOS差分低噪声放大器结构.基于该技术,采用0.35μmCMOS工艺设计了一种工作在5.8GHz的低噪声放大器.结果表明,在考虑了各种寄生效应的情况下,该低噪声放大器可以在0.75V的电源电压下工作,其功耗仅为2.45mW.在5.8GHz工作频率下:该放大器的噪声系数为2.9dB,正向增益S21为5.8dB,反向隔离度S12为-30dB,S11为-13.5dB.     

宽带单片低噪声反馈放大器

研制了0.6～6GHz单片GaAs FET低噪声反馈放大器。在该频带内,放大器芯片具有6dB增益,4dB左右的噪声系数。在1/2I_(ds)下,获得增益8dB,1dB增益压缩点为21dBm。以目前正在研制的1～10GHz两级单片芯片为例,讨论了这种放大器的设计,该放大器还可以进行级联,获得的总增益最高为50dB左右,纹波±1.5dB。     

S波段低噪声放大器CAD设计

介绍了S波段低噪声放大器 (LNA)的设计原理 ,对影响电路稳定性和噪声性能的、易被忽视的因素进行了详细分析。与以往同类文章有很大不同 ,文中重点分析实际电路可能产生的非连续性、寄生参数效应等因素对电路各个性能指标的影响 ,并针对这些因素进行软件仿真计算 ,最后给出工作带宽为 2 .0～ 4.0GHz、增益G >2 2dB、噪声系数NF <0 .7dB的两极低噪声放大器的仿真结果和最终的微带电路     

一种采用新型复合沟道GaN HEMTs低噪声分布式放大器

设计研制了一种新型的低噪声分布式放大器,采用了栅长为1μm的低噪声复合沟道Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMT (CC-HEMT). 给出了低噪声分布式放大器的仿真和测试结果. 测试结果显示低噪声分布式放大器在2~10GHz频率范围内,输入和输出端口驻波比均小于2.0,相关增益大于7.0dB,带内增益波纹小于1dB . 在2~6GHz频率范围内,噪声系数小于5dB;在2~10GHz频率范围内,噪声系数小于6.5dB; 测试结果与仿真结果较吻合.     

0.18-um CMOS 3.1-10．6GHz超宽带低噪声放大器设计

介绍了一种基于0．18-um CMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器。在3．1～10．6GHz的频带范围内对它仿真获得如下结果：最高增益12dB；增益波动小于2dB；输入端口反射系数S11小于-10dB；输出端口反射系数S22小于-15dB；噪声系数NF小于4．6dB。采用1．5V电源供电，功耗为10．5mW。与近期公开发表的超宽带低噪声放大器仿真结果相比较，本电路结构具有工作带宽大、功耗低、输入匹配电路简单的优点。     

S波段低噪声放大器设计

首先分析了低噪声放大电路的稳定性,功率增益及噪声系数的影响因素及改进方法;然后设计了一个中心频率为2.45 GHz,工作带宽为100MHz的S波段低噪声放大器.仿真结果表明,该放大器的噪声系数小于1 dB,功率增益大于28 dB,增益平坦度小于1 dB,输入/输出驻波比小于2:1.通过传统的电路板制作工艺实际制作了放大器电路,测试结果和仿真结果较一致.     

一种采用新型复合沟道GaN HEMTs低噪声分布式放大器

设计研制了一种新型的低噪声分布式放大器,采用了栅长为1μm的低噪声复合沟道Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMT(CC-HEMT).给出了低噪声分布式放大器的仿真和测试结果.测试结果显示低噪声分布式放大器在2～10GHz频率范围内,输入和输出端口驻波比均小于2.0,相关增益大于7.0dB.带内增益波纹小于1d8.在2～6GHz频率范围内,噪声系数小于5dB;在2～10GHz频率范围内,噪声系数小于6.5dB;测试结果与仿真结果较吻合.     

S波段低噪声放大器的分析与设计

介绍了S波段低噪声放大器（LNA）的设计原理和流程。对影响电路稳定性和噪声性能的、易被忽视的因素进行了详细分析。文中重点分析实际电路可能产生的非连续性、寄生参数效应等因素对电路各个性能指标的影响，并针对这些因素进行了软件仿真计算，最后给出了放大器的仿真结果和最终的微带电路。放大器设计为两极结构，采用GaAsFET器件和双电源电路设计形式，达到了预定的技术指标，工作带宽2．0～4．0GHz，增益G〉22dB，噪声系数NF〈0．7dB。     

全波段毫米波低噪声放大器

SPACEKLABS研制成这种最新的低噪声放大器在毫米波段 ,33～ 5 0GHz(WR - 2 2 )和 4 0～ 6 0GHz(WR - 19)能够提供全波段的性能。在此频段风 ,典型增益为 18～ 2 0dB ,最小噪声系数为 3dB。在 +8～ +11VDC时 ,DC为 5 0mA。全波段毫米波低噪声放大器@一凡     

应用于5GHz频段带ESD保护的可变增益低噪声放大器

本文给出了应用于5GHz频段的可变增益低噪声放大器。详细分析了输入寄生电容对源极电感负反馈低噪声放大器的影响,给出了一种新的ESD和LNA联合设计的方法,另外,通过在第二级中加入一个简单的反馈回路实现了增益的可变。测试结果表明： 可变增益低噪声放大器增益变化范围达25dB (-3.3dB～21.7dB),最大增益时噪声系数为2.8dB,最小增益时三阶截点为1dBm,在1.8V电源电压下功耗为9.9mW。     

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier (VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB (-3.3 dB to 21.7 dB) variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.     

Design of Low Power 2.4GHz CMOS Cascode LNA with Reduced Noise Figure for WSN Applications

In this paper, a narrowband cascode Low Noise Amplifier (LNA) with shunt feedback is proposed. A typical inductively degenerated cascode LNA can be treated as a Common Source-Common Gate (CS-CG) two stage LNA. The series interstage inductance is connected between CS-CG stages to increase the power gain. An additional inductance which is connected at the gate of CG stage is used to cancel out the parasitic capacitance of CG stage therefore reduces the noise figure of CG stage. The shunt feedback is used to improve the stability and input impedance matching. This configuration provides better input matching, lower noise figure, low power consumption and good reverse isolation. The proposed LNA exhibits the gain of 13 dB, input return loss of ?11 dB, noise figure of 2.2 dB and good reverse isolation of ?42.8 dB at a frequency of 2.4GHz using TSMC 0.13 μm CMOS technology. It produces gain and noise figure better than conventional cascode LNA. The proposed LNA is biased in moderate inversion region for achieving sufficient gain with low power consumption of 1.5mW at a supply voltage of 1.5V.     

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

This paper presents an integrated LNA for millimeter-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for ldquocorrect-by-constructionrdquo design at mm-wave frequencies and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with a NF of 6.5 dB, while drawing 26mA per stage from 1.65 V. Output is 3.8 dBm. At , each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB, respectively. Measured results are in excellent agreement with simulations, proving the effectiveness of the proposed design methodology. A custom set-up for mm-wave NF measurement is also extensively described in the paper.     

低功耗CMOS低噪声放大器的分析与设计

基于TSMC 0.18μm CMOS工艺,设计了一种低功耗约束下的CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在共源晶体管的栅源间并联一个电容,以优化噪声;并引入一个电感,与级间寄生电容谐振,以提高增益;通过减小晶体管的尺寸,实现了低功耗。模拟结果表明,在2.45 GHz工作频率下,增益大于14 dB,噪声系数小于1 dB,直流功耗小于2 mW。     

Capacitor Cross-Coupled Fully-differential CMOS Folded Cascode LNAs with Ultra Low Power Consumption

This paper proposes a fully-differential folded cascode low noise amplifier (LNA) for 5.5 GHz receiver in 180 nm CMOS technology. By improving folded cascode with an additional inductance connected at the gate of CG stage to cancel parasitic capacitance and then employing capacitor cross-coupled technique as a negative feedback in the proposed LNA, the performance of the LNA can be improved significantly in terms of gain (S21) and noise figure (NF) compared with the conventional fold cascode LNA. Furthermore, the DC power consumption of the LNA is further reduced with forward body bias topology. The measurements show the proposed LNA achieves 16.5 dB power gain, a NF of 1.53 dB, good input/output matching with the S11 and S22 are less than \(-\) 15 dB. And the operating voltage is only 0.5 V with ultra-low power consumption of 0.89 mW.     

Noise parameters for design of MMIC HEMT LNA

The letter gives the noise parameters of MOVPE HEMTs or the design of MMIC HEMT low-noise amplifiers. An example of the design of an HEMT LNA is given using these parameters. The MMIC LNA has been fabricated and exhibits a 2.3+or-0.2 dB noise figure with an associated gain of 12+or-2 dB in the 12-16 GHz frequency range. The measured performance is within 0.5 dB of the simulation.<>     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

一种用于地面和有线接收机的宽带低噪声放大器

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

2～12 GHz CMOS超宽带低噪声放大器设计

提出了一种基于双反馈电流复用结构的新型CMOS超宽带(UWB)低噪声放大器(LNA),放大器工作在2～12 GHz的超宽带频段,详细分析了输入输出匹配、增益和噪声系数的性能。设计采用TSMC 0.18μm RF CMOS工艺,在1.4 V工作电压下,放大器的直流功耗约为13mW(包括缓冲级)。仿真结果表明,在2～12 GHz频带范围内,功率增益为15.6±1.4 dB,输入、输出回波损耗分别低于-10.4和-11.5 dB,噪声系数(NF)低于3 dB(最小值为1.96 dB),三阶交调点IIP3为-12 dBm,芯片版图面积约为712μm×614μm。