基于SPARC V8体系的电子记帐终端设备研究

阐述了一款基于SPARC V8体系架构微处理器内核的SoC芯片的设计,该SoC芯片主要的目标应用领域是电子记帐终端设备,芯片内部集成了硬件浮点运算单元和大量的外部设备,以单芯片方案解决了以前实现同样功能的整机系统方案,既节省了应用系统成本,又提高了系统的可靠性。该芯片的设计成功使得“中国芯”家族又增添了一位新成员。     

C波段160W连续波GaN HEMT内匹配功率器件研制

基于GaN功率器件工艺自主研发的大栅宽GaN高电子迁移率晶体管(HEMT)管芯,采用内匹配技术和宽带功率合成技术相结合的方法,研制出了一款C波段160 W连续波GaN HEMT内匹配功率器件。通过优化管芯的结构,设计出了满足连续波使用要求的大功率GaN管芯,然后进行了内匹配器件的设计,在设计中首先采用负载牵引法进行了器件参数提取,并以此为基础设计了阻抗变换网络进行阻抗变换和功率合成。研制出了工作频率为4.4~5.0 GHz、工作电压32 V、连续波输出功率大于160 W、功率附加效率大于50%、功率增益大于12 dB的GaN HEMT内匹配功率管,具有广阔的工程应用前景。     

单片机教学系统驱动芯片测试装置的设计

针对DTHS-A单片机实验平台的日常维护需要设计了该测试装置,该装置能够快速的检测实验电路中驱动芯片是否正常,与传统方法相比,节约了维护的时间,提高了检测效率.该装置以STC15F2K61S2为控制核心,通过按键与拨码开关来选择对应芯片,通过液晶显示与LED指示芯片是否正常,同时具有过流保护功能.     

超大面积芯片烧结技术研究

随着半导体大功率器件的发展,芯片的散热一直是制约功率器件发展的因素之一。而器件内部散热主要是通过芯片背面向外传导,芯片焊接工艺是直接影响器件散热好坏的关键因素之一,合金焊料的一个显著优点就是其导热性能好,因此在散热要求高的大功率器件中使用较为广泛(如Au80Sn20、Au99.4Sb0.6等),但由于合金焊料烧结后会产生较大的残余应力,在尺寸大于8 mm×8 mm的芯片上,烧结工艺应用较少。文章针对11.5 mm×11.5 mm超大面积芯片进行金锡合金烧结试验,经过对应力产生的原因进行分析,从材料、封装工艺等方面采取措施来降低缓释应力,并对封装产品进行可靠性考核验证。试验结果表明,没有芯片存在裂纹、碎裂现象,产品通过了可靠性验证。     

A new type of demountable optical device for coupling single-mode planar waveguides to a multifiber array using passive alignment

A novel demountable optical device is developed for coupling single-mode waveguides to a multifiber array using passive alignment. This device is fabricated by forming V-grooves on a waveguide chip and precisely molding both end portions of the chip. The 1/spl times/8 coupling device exhibits a low insertion loss of 10.7 dB and a small loss change of /spl plusmn/0.2 dB for 100 reconnections.     

MOEMS chip-level optical fiber interconnect

A package design, fabrication process, and assembly process to hermetically seal the microstructure area of a microoptoelectromechanical system (MOEMS) at the chip level is presented and evaluated. The packaged chip is fabricated using the Bosch deep reactive ion etching (DRIE) process on silicon on insulator (SOI) substrates. The packaging structures are formed during the batch fabrication of the MOEMS device. A hermetic seal is formed via an indium solder ring around the perimeter of the MOEMS chip that span channels etched in the silicon for optical fibers. The seal is made between the device chip, metallized optical fibers, and a cap chip with a fluxless soldering process. The integrity of the package is evaluated through die shear, fiber pull, and highly accelerated life testing (HALT).     

超薄芯片叠层封装器件热可靠性分析

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。     

高压BCD集成电路中高压功率器件的设计研究

高压功率集成电路的设计与制造因其具有的高技术难度而极具挑战性。所谓高压功率集成电路 (HV-PIC) ,是指将需承受高电压 (需达数百伏 )的特定功率晶体管和其它低压的控制电路部分兼容 ,制作在同一块 IC芯片上。文中以器件模拟软件 Medici为工具 ,用计算机仿真的方法 ,研究了高压 BCD电路中高压功率器件的设计问题 ,其中包括器件结构、掺杂浓度、结深等主要参数及其它一些技术因素对器件耐压的影响 ,并给出了相应物理意义上的分析。根据这一设计 ,在国内进行了一块高压功率 BCD集成电路的试制 ,经测试 ,耐压超过 660伏 ,输出功率 40 W,且电路的其它器件参数达到设计值 ,IC电路整体功能正常 ,所有参数达标     

Simulating the dynamic electrothermal behavior of power electroniccircuits and systems

The simulator solves for the temperature distribution within the semiconductor devices, packages, and heat sinks (thermal network) as well as the currents and voltages within the electrical network. The thermal network is coupled to the electrical network through the electrothermal models for the semiconductor devices. The electrothermal semiconductor device models calculate the electrical characteristics based on the instantaneous value of the device silicon chip surface temperature and calculate the instantaneous power dissipated as heat within the device. The thermal network describes the flow of heat from the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the semiconductor device models. The thermal component models for the device silicon chip, packages, and heat sinks are developed by discretizing the nonlinear heat diffusion equation and are represented in component form so that the thermal component models for various packages and heat sinks can be readily connected to one another to form the thermal network     

Effects on VLSI Yield of Doubly-Stochastic Impurity Distributions

An expression is derived for the doubly-stochastic distribution of the number of impurities in the base region of a bipolar transistor; the distribution results from uncertainty in ion implantation parameters. Expressions are derived for device yield, and VLSI (very large scale integration) chip yield with an N-bit parity check. These derivations can be extended to other devices in a straightforward manner. As an example, calculations have been performed using specific parameters, which have led to the following observations: 1. The doubly stochastic effect is most sensitive to uncertainty in the straggle (standard deviation) of the emitter impurity distribution. 2. Uncertainty of the order of 5% in an implantation parameter causes substantial broadening of the distribution of impurities, for the case considered. 3. Device yield decreases rapidly for dimensions less than a well-defined threshold (? 0.75 ?m for the case considered). 4. Chip yield, without a parity check, exhibits a threshold effect at device yield = 1-1/Nchip.(Nchip ? number of devices per chip.) The device yield must exceed this threshold to produce large chip yields. 5. The use of a parity check reduces the device yield threshold to 1-10/NChip. Use of fewer bits per parity check reduces the threshold further. 6. For the example considered, the minimum device dimensions for large chip yields is of the order of 1 to 1.5 ?m, using a 16-bit parity check. The minimum device size for reliable system performance for other cases will depend upon specific device parameters.     

倒装焊器件封装结构设计

倒装焊是今后高集成度半导体的主要发展方向之一。倒装焊器件封装结构主要由外壳、芯片、引脚(焊球、焊柱、针)、盖板(气密性封装)或散热片(非气密性封装)等组成。文章分别介绍外壳材料、倒装焊区、频率、气密性、功率等方面对倒装焊封装结构的影响。低温共烧陶瓷(LTCC)适合于高频、大面积的倒装焊芯片。大功率倒装焊散热结构主要跟功率、导热界面材料、散热材料及气密性等有关系。倒装焊器件气密性封装主要有平行缝焊或低温合金熔封工艺。     

Surface-mountable EMC monopole chip antenna for WLAN operation

A novel surface-mountable monopole chip antenna having an electromagnetic compatibility (EMC) property is presented. In addition to the radiating strip on the chip base of the antenna, a ground portion is added on the side surfaces of the chip base. The antenna ground portion is to be grounded to the system ground plane of the mobile device for practical applications. The antenna ground portion can function as an effective shielding wall between the antenna and the nearby electronic components in the device. In this case, the nearby components can be placed in close proximity to the antenna, with small effects on the antenna performances. That is, the proposed antenna is EM compatible with the nearby components. In addition, the proposed antenna is surface-mountable onto the system circuit board of the mobile device, which reduces the packaging cost of the device. The proposed antenna applied to a smart phone or Personal Digital Assistant (PDA) phone for WLAN operation in the 2.4 GHz band is studied in the paper.     

ATE射频测试板低成本解决方案

近年来国内无线通讯市场发展迅猛,射频芯片的出货量也快速增长,射频芯片不同于其他SoC芯片,往往是市场周期短,更新速度快,这给芯片的量产测试带来挑战,ATE射频测试板作为测试的重要组件,成为制约测试开发和成本的最关键因素,ADVANTEST推出的低成本射频测试板兼顾了开发效率和测试成本的平衡性,给射频芯片的量产测试带来了...     

定时输出电源控制装置软件设计

以单片机Mega16芯片为核心,以时钟专用芯片1307为时基,以高压光耦驱动大功率可控硅为执行器件,设计了一种多时段可调定时输出电源控制装置。在阐述了定时输出电源控制装置的整机工作过程的同时,重点分析了定时输出电源控制装置的软件设计。该装置用于定时段运行的大功率设备的电源控制,经实践应用证明,可减少工作量,节能减排,且效果良好。     

微通道式PCR芯片温度的研究

微通道式PCR芯片是对DNA扩增的新方法，通过样品试剂在三个温区间的流动，实现对试剂中特定DNA片段的几何级数扩增。研究了一种新型微通道式PCR芯片，利用有限元技术，对芯片上热区的温度梯度和均匀性进行了计算，对影响PCR反应的三种温度因素作出了定量分析。另外，针对传感器和加热器的外形、放置以及加热区的不均匀化，采取了系列优化措施，计算了薄膜电阻功率和电阻参数，改善了芯片的热特性，提高了其倍增的效率。     

Recoverable ionic contaminant induced failures on n-channel memory products

For an n-channel MOSFET device technology, thick oxide threshold voltage degradation on a device adjacent to a thin oxide device with exposed gate oxide and tapers frequently causes chip failure. If the thin gate oxide and tapers are completely covered, then threshold voltage stability can be attained using phosphosilicate glass to getter ionic contaminants. A first order theory is proposed that relates circuit topology, electrical requirements, and ionic contaminant drift in oxides to chip failure. The model predicts the hierarchy of failing circuits within a chip and the recovery of these failures when left on temperature-bias testing. The latter implies that burn-in conditions must be carefully chosen to avoid recovery during temperature-bias testing. Failure to do so will allow this failure mode to go undetected and result in overly optimistic reliability projections for application conditions.     

一种芯片静电感应破坏测试方法

目前,芯片静电感应破坏测试评价采用的是对最终形态产品进行测试,而在每个产品生产环节中,芯片同样受到静电感应破坏的影响.本文根据产品生产中的形态和芯片器件层在静电感应破坏时受到的影响,提出了一种新的芯片静电感应破坏测试方法.     

2TF:一种协同考虑过硅通孔和热量的三维芯片布图规划算法

 三维芯片由多个平面器件层垂直堆叠而成,并通过过硅通孔(TSV,Through Silicon Via)进行层间互连,显著缩短了互连线长度、提高了芯片集成度.但三维芯片也带来了一系列问题,其中单个过硅通孔在目前的工艺尺寸下占据相对较大的芯片面积,且其相对滞后的对准技术亦降低了芯片良率,因此在三维芯片中引入过多的过硅通孔将增加芯片的制造和测试成本.垂直堆叠在使得芯片集成度急剧提高的同时也使得芯片的功耗密度在相同的面积上成倍增长,由此导致芯片发热量成倍增长.针对上述问题,本文提出了一种协同考虑过硅通孔和热量的三维芯片布图规划算法2TF,协同考虑了器件功耗、互连线功耗和过硅通孔数目.在MCNC标准电路上的实验结果表明,本文算法过硅通孔数目和芯片的峰值温度都有较大的降低.     

深亚微米CMOS IC全芯片ESD保护技术

CMOS工艺发展到深亚微米阶段,芯片的静电放电(ESD)保护能力受到了更大的限制。因此,需要采取更加有效而且可靠的ESD保护措施。基于改进的SCR器件和STFOD结构,本文提出了一种新颖的全芯片ESD保护架构,这种架构提高了整个芯片的抗ESD能力,节省了芯片面积,达到了对整个芯片提供全方位ESD保护的目的。     

Advanced Packaging: The Redistributed Chip Package

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.