System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs

A VLSI architecture for the block matching motion estimation is described in this paper. The proposed architecture achieves 100% PE utilization and alleviates I/O bottleneck problem using small amount of distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirement. The overall computations are performed in pipelined manner and the data fill time for contiguous block is eliminated to increase throughput. The VLSI system implementation methodologies and the layouts are also described. Finally, the performances are evaluated and the advantages are outlined, compared to other architectures.     

System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache

Program transformations are a powerful way of optimizing given applications for lower power and higher performance. In this paper, we explore avenues for power reduction by program transformations using the real-time constraints. In the sequel, we discuss the effects of our methodology, for optimization of power, on cache related performance aspects. Our target applications are in the real-time multimedia applications domain implemented on programmable multimedia or DSP processors. The effectiveness of our approach in obtaining a low power implementation and real-time performance is illustrated on three real-life applications, viz. a MPEG-2 decoder, a QSDPCM video codec and a Voicecoder application. Our experimental results indeed show that we are able to obtain lower power and still achieve a real-time performance.     

面向低功耗优化设计的系统级功耗模型研究

随着嵌入式系统应用的普及,低功耗设计成为系统设计中的关键问题之一.本文提出了一个两层构架的系统级功耗模型,包括微体系结构层模型和体系结构层模型.微体系结构模型支持系统级硬件结构设计优化,体系结构模型则针对编译器的软件设计优化.微结构模型以部件的结构信息特征为依据,指令级模型以微结构模型为基础.试验证明,该模型可以满足嵌入式系统的高层设计要求.     

A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

Due to the growing demand of digital convergence, there is a need to have a video encoder/decoder (codec) that is capable of supporting multiple video standards on a single platform. High Efficiency Video Coding (HEVC), successor to H.264/MPEG-4 AVC, is a new standard under development that aims to substantially improve coding efficiency compared to AVC High Profile. This paper presents an efficient architecture based on a resource sharing strategy that can perform the quantization operation of the emerging HEVC encoder and six other video encoders: H.264/AVC, AVS, VC-1, MPEG-2, MPEG-4, and Motion JPEG (MJPEG). Since HEVC is still in the drafting stage, the proposed architecture is designed in such a way that any final changes can be accommodated into the design. The proposed quantizer architecture is completely division-free, as the division operation is replaced by shift and addition operations for all the codecs. The design is implemented on an FPGA and later synthesized in CMOS 0.18 μm technology. While working at 190 MHz, the design can decode a 1080p HD video at up to 61 frames per second. The multi-codec architecture is also suitable for low-cost VLSI implementation.     

几种主流视频编码方式的性能比较和分析

随着多媒体通信技术的不断发展,不同的组织提出了许多不同特点的编码方法。文中回顾并分析了当前一些主流的编码机制,通过峰值信噪比(PSNR)和最小察觉差(JND)对主流视频编码技术的质量性能进行了比较。通过比较发现,使用客观的PSNR标准时,H．264/AVC的各方面性能要好于现在使用的视频压缩标准,但选择主观的JND标准可能会略微影响不同编码的性能。     

嵌入式视频图像系统压缩算法的实现与优化

针对最新的嵌入视频编码器宏块Cache严重缺失,帧率低等问题,提出了运动估计算法的优化、像素插值优化以及利用Cache使用优化、SAD,EDMA进行数据搬移方法,提高了存储速度,并在TMS3206465DSP平台上实现了MPEG-4视频编码器.     

一种基于嵌入式IP内核模块的测试方法

嵌入式内核结构的测试正面临着新的挑战,需要提出有效的测试方法。针对IP内核模块测试所面临的技术难点,详细介绍了IP核模块实现测试所需要构建的硬件环境和完整的测试方法,并分析了由测试理论和方法而形成的国际公认标准IEEEP1500。     

一种基于嵌入式微处理器内核模块的测试

基于可复用的嵌入式IP内核模块的系统级芯片（SoC）设计方法使测试面临新的挑战。文章针对IP内核模块测试断面临的技术难点，介绍了IP核模块实现测试所需要构建的硬件环境和通用结构．并以嵌入ARM微处理器棱的SoC为例，提出了具体的测试解决方案。     

系统级可编程能力助力嵌入式应用

本文探讨了人们通常面对的嵌入设计挑战.并以实用的方式探讨如何运用PSoC芯片这种系统级的可编程能力克服这些挑战.     

Quality-Aware Techniques for Reducing Power of JPEG Codecs

This paper presents use of bit truncation and voltage overscaling to reduce the power consumption of JPEG codecs. Both techniques introduce errors which have to be compensated to minimize quality degradation. To handle the errors due to bit truncation, we propose a compensation scheme based on unbiased estimation of the truncation noise. For 4-bit truncation, such a scheme achieves 23% power savings for DCT with only 0.6dB drop in PSNR. To compensate for errors due to aggressive voltage scaling, we introduce an algorithm-specific technique which is based on exploiting the characteristics of the quantized coefficients after zig-zag scan. This technique is very effective in improving the PSNR performance with a small circuit overhead. A combination of the two techniques help achieve even higher power savings with only a modest increase in PSNR. For instance, a combination of 4-bit truncation and operating voltage of 0.78V results in 44% power reduction for DCT with a 1.8dB drop in PSNR performance of the JPEG codec.     

嵌入式平台H.264软件解码器的优化

对H.264视频压缩标准的基本档次参考代码进行优化,使其适用于嵌入武平台.对参考代码提出了算法和代码级别优化策略.算法方面采用熵解码码表分割、简化运动补偿运算、全零块跳过等方法.代码优化方面采取减少内存读写、建立静态表格、减少冗余判断等方法来减少运算复杂度.实验表明,优化后的代码移植到嵌入式ARM平台在没有采用汇编语言和硬件加速的情况下能达到很好的解码效率,可以满足一些嵌入式平台的应用需求.     

A Self Test Program Design Technique for Embedded DSP Cores

This paper describes a self test program design technique for embedded DSP cores. The method requires minimal knowledge of the core’s internals and minimal insertion of external LFSR hardware, without scan insertions. The test program consists of a small set of instructions which operate iteratively on pseudorandom data generated by the LFSRs to fully test the DSP core components. The method uses instruction-based test metrics and a program template as a blueprint to generate the test program. The self test scheme has been successfully applied on an industrial-strength DSP core and the results compare favorably to other methods using ATPG and pseudorandom BIST. Editor: C.E. Stroud Hani Rizk received his B.S./M.S. in Computer Engineering at Case Western Reserve University in 2002. He currently works at Intel Corporation in Oregon. Chris Papachristou has a Ph.D. from Johns Hopkins University. He is currently a Professor of Computer Engineering at Case Western Reserve University. His research interests are in Embedded Systems, CAD, Adaptive Hardware, Testing and Fault Tolerance. Francis G. Wolff has a Ph.D. from Case Western Reserve University in Computer Engineering and is also a researcher in the area of computer engineering.     

一种嵌入式视频处理电路设计

阐述了一种嵌入式视频处理电路的系统结构、设计和实现。文中设计采用高性能双核处理器和大规模可编程器件,通过高速总线实现TV/IR视频、雷达视频的采集和分类传输处理。具有高性能、多功能、一体化的特点,可靠性好、便于保障和维护,适用于地面、车载等显控终端中。     

基于ARM9的视频点播系统的的设计

在计算机技术和流媒体技术的快速发展下,视频点播(VOD)系统得到了广泛的应用,伴随着嵌入式技术和网络技术的发展,出现了基于嵌入式的视频点播系统,本文介绍了基于ARM9的嵌入式视频点播系统的组成,重点阐述了该系统的工作原理、设计方案、软硬件模块的实现方法。     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

适于嵌入式系统的视频去块效应算法

为了消除基于块编码的低码率视频压缩技术中\     

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

A twin-transistor random access memory (TTRAM) can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. Enhanced TTRAM (ET²RAM) applies the actively body-bias control technique to realize the low voltage array operation, and never require the negative voltage source. The ET2RAM can realize both 263 MHz at 0.8 V and 10.2 mW at 0.5 V random-cycle operation, higher cell efficiency, and process scalability. It also provides the simple control method suitable for the unified macro for system-level power management SoC with keeping the merits of TTRAM as CMOS compatibility     

Structural Fault Testing of Embedded Cores Using Pipelining

The purpose of this paper is to develop a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a bypass mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested because they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the accessibility (of the core input and output ports) is solved as a shortest path problem. Finally, a pipelined test schedule is made to overlap accessing input ports (to send test patterns) and output ports (to observe the signatures). The experimental results show higher fault coverage and shorter test time.     

一种基于嵌入式的视频音频采集系统

给出了一种基于嵌入式硬件平台和Linux操作系统,采用MPEG4视频压缩标准和PCM音频标准的视频和音频采集系统的实现方案。通过对硬件和软件的设计实现了数据的实时压缩和采集。给出了整个系统的逻辑结构,并分别详细论述了硬件和软件的设计流程,着重介绍了如何将MPEG4视频流和PCM音频流保存成AVI格式以及如何实现格式转换的过程。     

基于嵌入式Linux的网络视频实时监控系统

介绍一种基于嵌入式Linux的网络视频实时监控系统。该系统采用客户／服务器结构,应用MPEG-4硬编码压缩方案和RTP／RTCP协议,通过TCP／IP协议进行网络通信。实现了用户对单／多个网络摄像头的同时监控,还可进行远程控制和管理,并具有运动检测和报警联动功能。