基于内插的全数字二元鉴相相干延迟锁定环

提出一种基于内插的全数字二元鉴相相干延迟锁定环(C-DDLL),用于直接序列码分多址系统上行链路伪随机码的跟踪,对AWGN、多用户于扰以及非理想内插影响下的环路跟踪性能进行了分析与计算机模拟,最后给出了数值结果及分析。     

采用锁频环和锁相环联合捕获的载波跟踪

针对传统锁频环-锁相环跟踪算法中环路状态转换过渡中出现频率阶跃的问题,提出了一种采用锁频环和锁相环联合捕获的方式替代单一锁频环进行捕获的改进算法,同时对环路状态转换的门限进行了推导。仿真结果表明,改进的算法在转换过程中更加平稳,环路性能得到了优化。在信噪比为-10 dB且存在加加速度时跟踪环路在转换时没有出现频率阶跃,达到了设计目的。     

Application of Kalman filters with a loop delay in synchronization

Discrete-time Kalman filters under a loop-delay constraint suffer performance loss and cease to be optimal. In this letter, modified Kalman filters are proposed to compensate for loop delay. The proposed filter performance is similar to a Kalman predictor. The results are applied to synchronizer loop-filter, design. Closed form expressions for both the update gain and the performance values are derived for first- and second-order disturbance models     

Impact of NBTI induced variations on delay locked loop multi-phase clock generator

Negative bias temperature instability (NBTI) is a serious reliability concern for both analog and digital CMOS VLSI circuits. The shift in threshold voltage and reduction in drain current due to NBTI in p-channel MOSFETs are time, bias and temperature dependent. The degradation of the PMOS at any critical nodes in the circuit leads to the failure of the circuit immediately or in few months/year. The Delay-Locked-Loop (DLL) which is used as multi-phase clock generator for microprocessors, frequency synthesizers, time-to-digital converter (TDC) etc. reduces the phase error between output and reference clock until it is locked. The delay variations due to process, voltage and temperature fluctuations are governed by its feedback system. At start-up, the phase shift of the output clock should lie between 0.5 and 1.5 times the time period of the reference clock to achieve regular locking. The deviations from the above criteria due to NBTI degradation directly affect the control system and lead to erroneous locking. The NBTI-induced time-dependent variation in PMOS of the delay stage in voltage-controlled delay line (VCDL) of DLL affects the delay in each stage of VCDL and propagates as phase error to the output clock. This paper analyzes the impact of NBTI-induced time-dependent variations in Delay-Locked-Loop (DLL) based clock generators for the first time. The DLL is designed with 180 nm technologies with working frequency range from 75 MHz to 220 MHz. The time dependent variations in VCDL, the most sensitive blocks of DLL, are analyzed. It is observed that these time-dependent variations increase the phase error and the working of DLL is severely affected at the rearmost end of frequency range. The output clock gets deviated and observed to be locked late after π/2 or π radians from the nominal lock. It is essential to prevent DLL locking to an incorrect delay or false lock and to bring the output clock back to the correct position. An adaptive body bias circuit is proposed in this paper to reduce the impact of NBTI degradation and thereby to prevent erroneous locking in DLL.     

Behaviour of fractional loop delay zero crossing digital phase locked loop (FR-ZCDPLL)

This article analyses the performance of the first-order zero crossing digital phase locked loops (FR-ZCDPLL) when fractional loop delay is added to loop. The non-linear dynamics of the loop is presented, analysed and examined through bifurcation behaviour. Numerical simulation of the loop is conducted to proof the mathematical analysis of the loop operation. The results of the loop simulation show that the proposed FR-ZCDPLL has enhanced the performance compared to the conventional zero crossing DPLL in terms of wider lock range, captured range and stable operation region. In addition, extensive experimental simulation was conducted to find the optimum loop parameters for different loop environmental conditions. The addition of the fractional loop delay network in the conventional loop also reduces the phase jitter and its variance especially when the signal-to-noise ratio is low.     

基于双边沿触发计数器的低功耗全数字锁相环的设计

提出了一种低功耗、快速锁定全数字锁相环的设计方法。该文从消除因时钟信号冗余跳变而产生的无效功耗的要求出发,阐述了双边沿触发计数器的设计思想,提出了用双边沿触发计数器替代传统数字序列滤波器中的单边沿触发计数器的锁相环设计方案,以从降低时钟工作频率、减小工作电压和抑制冗余电路的开关活动性等方面降低系统的功耗;同时在环路中采用自动变模控制技术,以加快环路的锁定速度,减少相位抖动。最后采用EDA技术进行了该全数字锁相环的设计与实现,理论分析和实验结果表明其低功耗性、快速锁定性均有明显改善。     

基于FPGA的自适应锁相环设计

利用锁相环进行载波跟踪是获取本地栽波的一种重要方法,针对锁相环的噪声性能和跟踪速度不能同时达到最优的限制,在锁相环PLL中引入自适应模块,根据环路所处的环境自适应对PLL环路参数做出调整.设计中利用仿真软件MATLAB对自适应锁相环进行仿真,并在FPGA硬件板上利用VHDL编程实现.在载波信号为10 MHz、采样率为80 MHz的条件下,设计的自适应锁相环在噪声水平较小时跟踪速度提高了0.5 μs左右,在噪声水平较高时相位抖动降低了0.01 tad左右.     

基于FPGA的全数字锁相环的设计

简单介绍了全数字锁相环(ADPLL)的结构和工作原理,提出一种在FPGA的基础上可增大全数字锁相环同步范围的设计方法,并给出了部分verilog HDL设计程序的代码和仿真波形。     

基于FPGA的全数字锁相环的设计

简单介绍了全数字锁相环(ADPLL)的结构和工作原理,提出一种在FPGA的基础上可增大全数字锁相环同步范围的设计方法,并给出了部分verilog HDL设计程序的代码和仿真渡形.     

A high-resolution time interpolator based on a delay locked loopand an RC delay line

An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7-μm CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology     

基于ADF4106的锁相环设计

信号源作为一种通用测试仪器,是研制、检测与维护众多电子产品的必备工具,而频率合成是信号源的核心组成部分,对信号源整机的功能和指标起着决定性作用,锁相环频率合成可以产生高质量的频率,本设计利用锁相环基本原理,设计出了高性能的频率合成电路.本文详细介绍了某信号源二本振频率3.6GHz的锁相环设计,给出了系统原理图以及关键电...     

基于全数字锁相环的基波频率测量算法

本文提出了一种用于电能计量芯片的基波频率测量算法.其创新点是从系统设计出发,把基波频率测量与电能计量中过采样ADC的梳状积分级联抽取滤波(以下简称CIC)过程相结合,利用CIC、正交去调鉴频器、PI调节器和基波频率—CIC抽取率转换器共同构成一个全数字锁相环(以下简称ADPLL).该锁相环可以有效地抑制输入信号中的直流...     

基于科斯塔斯锁相环的光学零差相干接收技术

零差相干光通信能够实现极高的通信速率和接近量子极限的灵敏度,是新一代空间通信领域极具潜力的通信体制。以窄线宽激光器作为本振源,结合90°光学混频技术和科斯塔斯光学锁相环技术,实现了信号光的零差相干接收。试验结果表明,信号光和本振光经过90°光学混频后I、Q两路信号相位差保持90°,科斯塔斯光学锁相环可以长时间实现信号光和本振光之间的相位锁定,接收速率为2Gbps的二进制相移键控(BPSK)信号,试验结果表明,该接收机能够很好地实现基带信号解调。     

一种基于LMS迭代的环路延时估计算法

数字预失真技术是有效补偿射频功率放大器的非线性方案;然而,前向数据与反馈数据之间的延时估计是数字预失真系统的关键性问题,直接影响着非线性的补偿能力。在此基于滑动窗的相关运算,介绍一种整数倍的环路延时估计算法,同时基于LMS迭代逐个数据输入进行比较,提出了一种自适应小数倍的环路延时估计算法。最后对算法进行仿真验证,结果表明,经过整数倍的环路延时估计后,对于在[-T]s,Ts范围内的残余的小数倍延时,该算法均表现出优异的估计性能。     

基于FPGA的改进积分型位同步环设计

介绍了积分型位同步环的原理。针对相位抖动的问题,提出了积分型位同步环的改进方案。采用模块化的设计思想,利用VHDL语言设计了改进的积分型位同步环,并在Xilinx的FPGA器件XC3S200-4FT200上进行了实现。利用Modelsim6.0软件对改进前后的位同步环进行了仿真测试,仿真结果表明,改进的位同步环可有效减少相位抖动,满足性能要求。     

基于锁相环（PLL）L波段的频率合成技术

频率合成器是电子设备的核心部件,其性能的优劣影响电子设备的整体性能。本文研究了一种基于锁相环（PLL）L波段的锁相频率技术。其设计方案使用MC145152来实现锁相环路,外加环路滤波器LPF和压控振荡器VCO等器件来实现,具有较强的研究设计价值。     

A high-precision spread spectrum clock generator based on a fractional-N phase locked loop

A low jitter Spread Spectrum Clock Generator (SSCG) based on a fractional-N Phase Locked Loop (PLL) capable of generating various Electromagnetic Interference (EMI) reduction levels is proposed. A digital compensation filter is fully integrated in the design to prevent various triangular modulation profiles from being distorted by the prohibitively small PLL loop bandwidth. A simple but comprehensive logic design included in the digital filter provides independently controllable modulation frequency, f _m, and modulation ratio, δ_m within all modulation modes (up, down, center). The proposed SSCG is designed in a 0.18 μm CMOS standard cell library and operates at 72 MHz with f _m ranging from 58 to 112.5 kHz and δ_m ranging from 0.75 to 2 %.     

基于平均电流的双闭环APFC电路的设计

为有效消除电力电子设备的谐波干扰,基于UC3855设计了BOOST功率因数校正电路。主电路为减少功率损耗采用ZVT零电压辅助开关。控制电路采用双闭环平均电流模式。利用乘法器校正使输入电流接近正弦波并保持与电压同相位。通过小信号建模推导了电流环、电压环传递函数,配置了系统双环补偿校正网络的参数。最后通过MATLAB仿真和实验验证了设计的正确性。系统的动、稳态性能良好,功率因数接近为1。     

An integrated high resolution CMOS timing generator based on anarray of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 μm CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives