BIST-based test and diagnosis of FPGA logic blocks

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable     

嵌入式系统的在线自测试技术

嵌入式系统必须满足用户对其越来越高的安全性和可靠性的要求,作者首先审视了用于测试数字系统故障的各种在线可测试技术,然后重点讨论了一种将被广泛应用于嵌入式系统的在线测试技术－内建自测试技术。     

FPGA逻辑资源重配置测试技术研究

针对FPGA的逻辑资源测试,提出了一种内建自测试方法.测试中逻辑资源划分为不同功能器件,对应各个功能器件设计了相应的BIST测试模板.在此基础上进一步利用FPGA的部分重配置性能优化BIST测试过程,最终在统一的BIST测试框架下,采用相对较少的配置次数完成了逻辑资源固定故障的全覆盖测试.     

X-masking during logic BIST and its impact on defect coverage

We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.     

An effective logic BIST scheme based on LFSR-reseeding and TVAC

An effective logic built-in self-test scheme aiming at reducing the area overhead of IC testing and improving the fault average is proposed, which combines strategies of linear feedback shift register (LFSR)-reseeding with test vectors applied by circuit-under-test itself (TVAC). LFSR-reseeding technology is first applied to decrease the size of test set and the number of interior feedback wires, while TVAC technology is applied to decrease the number of stored seeds. An efficient LFSR-reseeding algorithm and a modified quick judgment method for path search are proposed. Experimental results for ISCAS 85 benchmarks demonstrate that the proposed method reduces the number of interior feedback wires more than 50% on average and can achieve full fault coverage with much less groups as well as area overhead compared with previous TVACs.     

A New FPGA for DSP Applications Integrating BIST Capabilities

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an FPGA, not only for the system functionality, but also for the system testing, while keeping the performance level required by current signal processing applications. This paper presents the new FPGA model, along with preliminary experimental results that clearly show the possible advantages at the system level of merging design and test in a reconfigurable device.     

An Accumulator-Based Compaction Scheme For Online BIST of RAMs

Transparent built-in self test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this paper the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. It is shown that in this way the hardware overhead, the complexity of the controller, and the aliasing probability are considerably reduced.      

基于Virtex 4 FPGA的全覆盖二倍线内建自测试

随着集成电路技术的发展,高集成度和高复杂度的器件不断出现,大规模集成电路的测试技术成为重要的研究方向。自建内测试方法是一种有效的系统级大规模集成电路FPGA测试方法。提出了一种基于Xilinx公司Virtex-4(V4)系列芯片全覆盖的FPGA二倍线内建自测试方法,该方法采用脚本生成Xilinx设计语言(XDL),对V4芯片二倍线进行全局布线,然后进行FPGA配置,施加测试向量,从而对固定故障或者桥接故障进行测试。同时给出了基于XC4VLX100芯片的实际测试结果,验证了该测试方法的正确性。     

虚拟FPGA逻辑验证分析仪的设计

随着FPGA技术的广泛使用,越来越需要一台能够测试验证FPGA芯片中所卜载电路逻辑时序是否正确的仪器。目前,虽然Agilent,Tektronix等大公刮生产的高端逻辑分析仪能够实现FPGA电路的测试验证功能,但此类仪器价格高昂,一般要十万、数十万人民币。所以,研究开发价格适中且具有逻辑分析仪和FPGA电路的测试验证功能的仪器是非常有价值的。     

利用单板机+FPGA实现对FPGA的在线配置

由于某雷达整机联调的需要,为了可以在雷达开机转动时在线配置测试更改后的FPGA调试程序,可以用单板机上存放的配置FPGA所需的bit文件通过CPCI总线访问另一片接口FPGA去配置主运算FPGA,从而解决了运行条件下实时调试程序的问题,还可以应用于多种模式分时复用FPGA的场合。     

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect

FPGA test cost can be reduced effectively by minimizing the number of test configurations. To realize it, a self-configurable structure was proposed before to test the cross-point-based switch box in FPGA. In this paper, a technique of partially self-configurable multiplexers is presented to reduce the test cost of completely multiplexer-based FPGA interconnect cost-efficiently. The additional self-configured structure, called test point here, is only added to the most efficient configuration ports, which is selected through analyzing test configurations, so the test cost can reduce with the minimal area overhead. It is shown that for testing all interconnect stuck-at faults in FPGAs like Virtex-II and Spartan-3 the test configurations can be reduced to 8 with merely about 1.2% area penalty.     

Layout techniques for FPGA switch blocks

This paper presents abstract layout techniques for a variety of field-programmable gate array switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks and good results for large switch blocks. We show how it is possible to transform universal switch blocks into a subset architecture by using the decomposition property of universal switch blocks. This allows universal switch blocks to exploit the same layout methodologies as presented for subset architectures.     

Designing via-configurable logic blocks for regular fabric

In this paper, we describe the design process of a via-configurable logic block for regular fabric. The block consists of a via-configurable functional cell and two via-configurable inverter arrays. A via-configurable functional cell can efficiently implement most commonly used CMOS static cells, and a via-configurable inverter array is efficient in implementing inverters, repeaters, and some pass-transistor logic. The cells have prefabricated transistors, contacts, and M1 wires. The M2 mask is fixed. All of the functions can be realized by customizing only an M1-M2 via mask. We construct a general-purpose fabric based on the via-configurable block and show its great flexibility in implementing a variety of functions. Compared to other fabrics based on look-up tables or programmable logic arrays, our fabric has much higher performance, smaller area, and lower power consumption.     

基于FPGA的简易逻辑分析仪设计

基于数字信号采集及数字示波器存储显示原理,并以AT89S52单片机和现场可编程门阵列(FPGA)组成的最小系统为核心,采用数字信号发生器模块、由模拟开关和A/D采样组成的信号并行采集电路、触发模块、数据储存模块和显示电路等构成简易逻辑分析仪.该分析仪的功能全面,价格低,能实时分析8路数字信号,具有很高的实用价值.     

Modular and rapid testing of SOCs with unwrapped logic blocks

Extensive research has been carried out for test planning of core-based system-on-a-chip devices. Most of the prior work assumes that all of the embedded cores are wrapped for test purpose. However, some designs may contain user-defined logic or cores that cannot be wrapped due to area constraints or timing violations. This paper discusses how these unwrapped logic blocks can be tested rapidly by adapting the TestRail architecture, which uses only the test control mechanism and the test instructions available through the IEEE 1500 standard for embedded core test. A new test scheduling algorithm, which facilitates a concurrent test of both unwrapped logic blocks and IEEE 1500-wrapped cores, is proposed, and experiments show that it outperforms a previous approach when the available number of tester channels and/or the number of unwrapped logic blocks are small.     

基于MCU的FPGA在线配置

针对FPGA器件的下载配置问题,介绍了一种基于MCU的FPGA在线配置的方法,并以ALTERA公司的CycloneII系列下的EP2C35为例, 结合FPGA的一般配置方法, 从基本原理、硬件设计、软件操作等几个方面较详细地提出一种如何利用单片机配合串行的Flash存储器实现对大容量FPGA芯片的被动串行(PS)方式的在线配置.并提出一种利用ARM7通过TCP/IP协议实现远程更新的方式.对于EP2C35的1.16MB大配置文件,采用这种方法只需1分30秒即可成功配置.     

一种电台中FPGA的可靠初始化逻辑设计

在机载通信领域,由于飞机体积、重量及功耗等要求,往往需要在一个独立电台设备上实现多种通信模式,同时受限于电台的成本、功耗等因素,通常各种通信模式功能依靠FPGA的动态加载来实现。实际工程中发现,当FPGA动态加载时,由于各版本的加载时间、复位管理、时钟管理、接口时序等不一致,非常容易出现偶发的加载后功能异常,此类问题现象随机,极难定位,很容易耗费大量的人力、物力及时间。为解决上述矛盾,提出一种适合在电台中使用的FPGA初始化逻辑设计,保证不同版本的FPGA加载后能稳定工作,提升电台工作的可靠性与稳定性。实践表明,该方法简单、可靠,具有非常强的工程推广意义。