驻极体传声器专用管的特性

1 传声器管结构及用途 驻极体传声器专用管简称为传声器管,在传声器中,它主要起阻抗变换作用,即利用结型场效应晶体管输入阻抗高,而输出阻抗低的特性,在声电转变过程中起接口作用。这类传声器,有漏极输出和源极输出两种不同形式。目前生产的各种型号的传声器,基本上都是属于漏极输出的。漏极输出时,肯定没有源极输出时那样稳定。这种漏极输出又跟传声器管的跨导（gfs）大小有着直接关系。 传声器管由一个结型场效应管和一个栅源极间的正向箝位二极管共同组成的简单组合器件,如图1所示。其中的结型场效应管通常都是N沟道耗尽型器件…     

应用一种新T形栅版图设计方法的AlGaN/GaN高电子迁移率晶体管

在蓝宝石衬底上制作AlGaN/GaN高电子迁移率品体管.由于使用了一种全新的T形栅电子束曝光版图,因此可以自由地改变T形栅的宽窄比(T形栅头部尺寸与栅长的比值)并优化T形栅的形状.所得的0.18μm栅长的器件,其特征频率(fT)为65GHz,T形栅的宽窄比为10.同时,测得的峰值跨导为287mS/mm,最大电流街度为980mA/mm.     

一种应用于PD的高精度限流保护调节电路

在POE(PowerOverEthernet)系统的终端受电设备中,限流保护调节电路保证了其稳定可靠工作。根据IEEE802.3af标准规定,受电设备开关电源启动到正常工作的过程中,电流要限制在100mA以内,在正常工作情况下电流要限制在390mA以下。本设计通过栅源比例电阻使采样功率管栅源电压与输出功率管的栅源电压保持一致,采样功率管精确采样输出功率管的电流值,采样电流经栅源比例电阻转换为电压后,调节输出功率管栅源电压,来完成PD(PowerDevice)限流保护。     

高温正向栅电流下Ti/Pt/Au栅SiC MESFET的栅退化机理

SiC MESFET器件的性能强烈依赖于栅肖特基结的特性,而栅肖特基接触的稳定性直接影响其可靠性.针对SiC MESFET器件在微波频率的应用中射频过驱动导致高栅电流密度的现象,设计了两种栅极大电流的条件,观察栅肖特基接触和器件特性的变化,并通过对试验数据的分析,确定了栅的寄生并联电阻的缓慢退化是导致栅肖特基结和器件特性退化,甚至器件烧毁失效的主要原因.     

100V高压CMOS工艺关键技术的研究

提出了一种新的双栅氧(dual gate oxide,DGO)工艺,有效提高了薄栅氧器件与厚栅氧器件的工艺兼容性,同时提高了高低压器件性能的稳定性.在中国科学院微电子研究所0.8μm n阱标准CMOS工艺基础上设计出高低压兼容的100V高压工艺流程,并流片成功.实验结果表明,高压n管和高压p管的关态击穿电压分别为168和-158V,可以在100V高压下安全工作.     

无结器件的单粒子辐射效应

介绍了一种新型沟道非均匀掺杂的双栅无结金属氧化物半导体场效应晶体管(MOSFET)。采用Sentaurus TCAD仿真软件对不同沟道掺杂浓度(NSC)的沟道非均匀掺杂双栅无结MOSFET和传统双栅无结MOSFET进行了电特性与单粒子辐射效应对比研究,并分析了不同源端沟道掺杂与源端沟道长度(LSC)下新型双栅无结MOSFET的单粒子辐射特性。仿真结果表明,新型双栅无结MOSFET的电学特性与传统双栅无结MOSFET相差不大,但在抗单粒子辐射方面具有优良的性能,在受到单粒子辐射时,可有效降低沟道内电子-空穴对的产生概率,漏极电流与收集电荷都低于传统无结器件,同时还可以降低寄生三极管效应对器件的影响。     

一种抗辐射加固功率器件──VDMNOSFET

采用 Si3N4- Si O2 双层栅介质及自对准重掺杂浅结 P+区研制出了一种抗辐射加固功率器件—— VDMNOS-FET (垂直双扩散金属 -氮化物 -氧化物 -半导体场效应晶体管 ) .给出了该器件的电离辐射效应及瞬态大剂量辐射的实验数据 ,与常规 VDMOSFET相比获得了良好的抗辐射性能 .对研制的 2 0 0 V VDMNOSFET,在栅偏压 +10 V,γ 总剂量为 1Mrad (Si)时 ,其阈值电压仅漂移了 - 0 .5 V,跨导下降了 10 % .在 γ瞬态剂量率达 1× 10 1 2 rad(Si) /s时 ,器件未发生烧毁失效 .实验结果证明 Si3N4- Si O2 双层栅介质及自对准重掺杂浅结 P+区显著地改善了功率 MOS器件的     

一种新型偏置栅MOS 管漂移区表面电压 和电场的分析模型

本文提出了偏置栅MOS管漂移区离子注入剂量对表面电压和PN结边界电场两者关系的一种新的分析模型，借助数学推导得到该模型的计算方程，通过仿真曲线图能清楚地看到它们之间的变化关系，同时说明提高偏置栅MOS管击穿电压的方法。     

一种P-GaN栅极结合槽栅技术的增强型HEMT

为了得到高击穿电压、高阈值电压的增强型GaN器件,提出了一种P型掺杂GaN(P-GaN)栅极结合槽栅技术的AlGaN/GaN/AlGaN双异质结结构.该器件的阈值电压高达3.4 V,击穿电压达738 V.利用Sentaurus TCAD进行仿真,对比了传统P-GaN栅与P-GaN栅结合槽栅的AlGaN/GaN/AlGa...     

一种抗辐射加固功率器件--VDMNOSFET

采用Si3N4-SiO2双层栅介质及自对准重掺杂浅结P+区研制出了一种抗辐射加固功率器件--VDMNOSFET(垂直双扩散金属-氮化物-氧化物-半导体场效应晶体管).给出了该器件的电离辐射效应及瞬态大剂量辐射的实验数据,与常规VDMOSFET相比获得了良好的抗辐射性能.对研制的200V VDMNOSFET,在栅偏压+10V,γ总剂量为1Mrad(Si)时,其阈值电压仅漂移了-0.5V,跨导下降了10%.在γ瞬态剂量率达1×1012rad(Si)/s时,器件未发生烧毁失效.实验结果证明Si3N4-SiO2双层栅介质及自对准重掺杂浅结P+区显著地改善了功率MOS器件的抗电离辐射及抗辐射烧毁能力.     

SiC肖特基栅JFET功率特性的研究

提出了一种新型结构的SiC结型场效应晶体管,采用肖特基接触替代P+型栅区,以降低SiC JFET的工艺复杂度,并提高器件的功率特性。建立了器件的数值模型,对不同材料和结构参数下的功率特性进行了仿真。结果表明,与PN结栅相比,肖特基栅结构可以有效降低SiC JFET的开态电阻;与常规结构的双极模式SiC JFET相比,在SiC肖特基栅JFET的栅极正偏注入载流子,同样可以有效降低器件的开态电阻,折中器件的正反向特性,但不会延长开关时间。     

JFET压磁电效应的理论分析

本文用标准的松弛方法研究了结型场效应晶体管的压磁电效应。利用准平面拉普拉斯方程及有限差分法计算了不同栅电压、漏电压以及n沟道硅器件不同宽长比的压力灵敏度和磁灵敏度。在P0,B=0,器件宽长比为W/L=1/2-1时,电流性压力灵敏度约为:2.5％cm2/N。据此,提出了一种有良好工作稳定性及噪声性能的力学量敏感器件结型场效应力敏管(Junction field effect-pressure sensor)。     

一种积累型槽栅超势垒二极管

提出了一种积累型槽栅超势垒二极管,该二极管采用N型积累型MOSFET,通过MOSFET的体效应作用降低二极管势垒。当外加很小的正向电压时,在N+区下方以及栅氧化层和N-区界面处形成电子积累的薄层,形成电子电流,进一步降低二极管正向压降;随着外加电压增大,P+区、N-外延区和N+衬底构成的PIN二极管开启,提供大电流。反向阻断时,MOSFET截止,PN结快速耗尽,利用反偏PN结来承担反向耐压。N型积累型MOSFET沟道长度由N+区和N外延区间的N-区长度决定。仿真结果表明,在相同外延层厚度和浓度下,该结构器件的开启电压约为0.23 V,远低于普通PIN二极管的开启电压,较肖特基二极管的开启电压降低约30%,泄漏电流比肖特基二极管小近50倍。     

基于BJT和JFET的AGC电路的设计和实现

设计了自动增益控制电路,能够使放大电路的增益自动随信号强度的变化而调整。该电路通过采用改变BJT的直流工作状态来改变BJT的电流放大系数β,实现电阻分压以及改变JFET的栅源电压来控制放大器电阻的大小。设计的自动增益控制电路阐述了BJT分压、JFET变阻以及AGC电路的工作原理,实现了可控增益范围大约为40dB,对现实教学和应用都有很好的借鉴意义。     

Performance of GaAs JFET at a cryogenic temperature for application to readout circuit of high-impedance detectors

A GaAs junction field effect transistor (JFET) is a promising candidate for the cryogenic electronics of high-impedance sensitive photoconductors because of its low-noise at low frequencies. This GaAs JFET has advantages compared with other type of FETs, such as no kink phenomena or hysteresis in its current-voltage (I-V) characteristics, small gate leakage currents, and minute capacitance. We report on the noise spectra and leakage current of a SONY n-type GaAs FET in a high-impedance configuration where the gate terminal was surrounded by high-impedance devices at a cryogenic temperature, i.e., 4.2 K. In the high-impedance configuration, we obtained a low noise level and low leakage current of 0.5 /spl mu/V/Hz/sup 1/2/ at 1 Hz and 4.6/spl times/10/sup -19/ A. This result implies that the GaAs JFET is suitable for cryogenic readout electronics. We also discuss the source of the random telegraph signal and the 1/f noise in the GaAs JFET at cryogenic temperatures.     

Enhanced Sensitivity of Small-Size (With 1-$mu hbox{m}$ Gate Length) Junction-Field-Effect-Transistor-Based Germanium Photodetector Using Two-Step Germanium Epitaxy by Ultrahigh Vacuum Chemical Vapor Deposition

In this letter, we demonstrate a scalable (with gate length of 1 mum) Ge photodetector based on a junction field-effect-transistor (JFET) structure with high sensitivity and improved response time. To overcome the low-detection-efficiency issue of typical JFET photodetectors, a high-quality Ge epilayer, as the gate of JFET, was achieved using a novel epigrowth technique. By laser surface illumination of 3 mW on the Ge gate, an I _ON/I _OFF ratio up to 185 was achieved at a wavelength of 1550 nm for the first time. In addition, the device shows a temporal response time of 110 ps with a rise time of 10 ps, indicating that the scalable Ge JFET photodetector is a promising candidate to replace large-size photodiodes in future optoelectronic integrated circuits and as an image sensor integrated with a CMOS circuit for its comparable size in respect to modern MOSFETs.     

Fabrication and characterization of polymeric p-channel junction FETs

Polymer materials are attracting more and more attention for the applications to microelectronic/optoelectronic devices due to their flexibility, lightweight, low cost, etc. In this paper, fabrication and characterization of a polymer junction field-effect transistor (JFET), using poly (3,4-ethylenedioxythiophene) poly (styrenesulfonate) (PEDT/PSS) as the channel and poly (2,5-hexyloxy p-phenylene cyanovinylene) (CNPPV) as the gate layer, are reported. The all-polymer JFET was fabricated by the conventional ultraviolet (UV) lithography techniques. The fabricated device was measured and characterized electrically. In the meantime, the comparisons were listed between polymer JFET and analogous inorganic semiconductor counterparts. Its pinch-off voltage reaches 1 V that is in the applicable range, and the current is -13.8 /spl mu/A at zero gate bias. It demonstrates that the device operates in a very similar fashion to its conventional counterparts.     

Pinch-Off Voltage-Adjustable High-Voltage Junction Field-Effect Transistor

In this letter, a novel type of high-voltage n-channel junction field-effect transistor (JFET) was designed using a conventional n-channel laterally diffused metal-oxide-semiconductor (n-LDMOS) without changing any step in the process. High-voltage JFET can be a start-up device in power factor correction, dc-ac converters, and ac-dc converters for providing a self-powered circuit and minimizing standby power losses without gate control because of its negative threshold voltage. Experimental results show that an n-LDMOS with this JFET structure can achieve a reverse blocking voltage of more than 700 V with very low leakage current. The pinch-off voltage can be designed by changing n-well width to meet the circuit requirement.     

Ti-IF和Ti+Nb+P-IF钢连退板的析出物与织构研究

对普通Ti-IF钢和高强Ti+Nb+P-IF钢连退板分别进行了析出物分析与微观织构检测。结果表明:普通IF钢中有较多粗大的TiN、Ti(C,N)和Ti4C2S2析出物,形成了较强的γ纤维织构;高强IF钢中发现有许多Fe(Nb,Ti)P相析出,并弥散分布大量细小的(Nb,Ti)C析出物,促使晶粒细化,γ纤维织构减弱。     

Optimum design in a JFET for minimum generation–recombination noise

Generation–recombination noise caused by the presence of deep level traps in the depletion regions of a junction field effect transistor (JFET) is analyzed. An analytical expression which includes all the elements that influence the process was used. A numerical procedure allowed us to calculate with high precision the magnitudes necessary to evaluate the noise spectral density. The doping profile and gate bias voltage were selected among all the factors involved to analyze their effects on the noise. Important differences were appreciated when uniform and ion-implanted profiles were used for JFET design. Finally, it is shown that the behavior of the noise spectral density as a function of the gate voltage depends on the characteristics of the device.