Low-frequency noise in TFSOI lateral n-p-n bipolar transistors

Low-frequency (1/f) noise is characterized as a function of base current density (J_B) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to J_B ^1.8 for J_B<0.4 μA/μm², which suggest that the noise in these devices is primarily dominated by a uniform distribution of noise sources across the emitter-base area. However in the high current region of operation (J_B>0.4 μm²), the noise bias dependence shifts to J_B ^1.2, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region     

1/f noise in CMOS transistors for analog applications

Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two “low noise” CMOS processes of 2 μm and 0.5 μm technologies are compared and it is found that the more advanced process, with 0.5 μm technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits     

A fully monolithic 260-/spl mu/W, 1-GHz subthreshold low noise amplifier

A micro-power complementary metal oxide semiconductor (CMOS) low-noise amplifier (LNA) is presented based on subthreshold MOS operation in the GHz range. The LNA is fabricated in an 0.18-/spl mu/m CMOS process and has a gain of 13.6 dB at 1 GHz while drawing 260 /spl mu/A from a 1-V supply. An unrestrained bias technique, that automatically increases bias currents at high input power levels, is used to raise the input P1dB to -0.2 dBm. The LNA has a measured noise figure of 4.6 dB and an IIP3 of 7.2 dBm.     

Flicker noise in CMOS transistors from subthreshold to stronginversion at various temperatures

Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation     

Effect of substrate biasing on Si/SiGe heterostructure MOSFETs for low-power circuit applications

We have investigated the effect of substrate biasing on the subthreshold characteristics and noise levels of Si/Si/sub 1-x/Ge/sub x/ (x=0,0.15,0.3) heterostructure MOSFETs. A detailed analysis of the dependence of threshold voltage, off-state current, and low-frequency noise level on the substrate-source (V/sub bs/) biasing showed that SiGe heterostructure MOSFETs offer a significant speed advantage, an extended subthreshold operation region, a reduced noise level, and reduced bulk potential sensitivity compared to Si bulk devices. These experimental results demonstrate that SiGe heterostructure MOSFETs render a promising extension to the CMOS technologies at the low-power limit of operation, eventually making the micropower implementation of radio frequency (RF) functions feasible.     

Body bias dependence of 1/f noise in NMOS transistors fromdeep-subthreshold to strong inversion

Dependence of 1/f noise on the body-to-source junction bias voltages (V_BS) between -2.5 and 0.5 V for 0.25-μm NMOS transistors is reported. In subthreshold, 1/f noise is reduced by about one order of magnitude, when the body-to-source junction is forward biased by 0.5 V (V_BS) compared to that for V_BS=0 V, which is due to increased depletion layer capacitance as well as possibly due to an increased average distance between oxide traps and carriers caused by the forward bias. On the contrary, in strong inversion, 1/f noise remains almost constant for the entire V_BS range     

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.     

Back-gate bias effect on the subthreshold behavior and theswitching performance in an ultrathin SOI CMOS inverter operating at 77and 300 K

The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V_B=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V_B=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field     

Reducing MOSFET 1/f noise and power consumption by switched biasing

Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 μm CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%     

55 nm SONOS闪存单元的1/f噪声特性研究

基于55 nm ULP CMOS工艺来制备SONOS闪存单元,并通过1/f噪声测试等方式对测试单元的器件特性进行表征。基于1/f噪声表征和转移特性,分析了编程态和擦除态下SONOS闪存单元内部缺陷水平的变化规律与机制。针对1/f噪声与亚阈值特性的缺陷水平出现矛盾的现象,引入NBTI中的双阶段模型进行阐述,进一步分析1/f噪声测试环节对SONOS器件的影响。     

Analysis of temporal noise in CMOS photodiode active pixel sensor

Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise     

Ultra-low-power DLMS adaptive filter for hearing aid applications

We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.     

CMOS图像传感器像素中MOSFET晶体管的栅感应噪声原理及分析

提出一种CMOS图像传感器像素中MOSFET晶体管的栅感应噪声原理.分析表明MOSFET工作于强反型区的栅感应噪声比工作于亚阈值区明显,但当施加在栅极电压达到3V时,随着ω/ωT比值的增加,MOSFET工作于亚阈值区的栅感应噪声比工作于强反型区明显.同时详细分析了有源像素(APS)中的RESET晶体管的栅感应噪声的影响并提出抑制栅感应噪声的电路.     

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.     

电应力对GaAlAs红外发光二极管低频噪声的影响

在宽范围偏置条件下,测量了电应力前后GaAlAs红外发光二极管（IRED）的低频噪声,发现应力前后1／f噪声随偏置电流变化的规律没有改变,但应力后1／f噪声幅值比应力前增加大约i00倍。基于载流子数和迁移率涨落的理论分析表明,GaAlAs IRED的1／f噪声在小电流时反映体陷阱特征,大电流时反映激活区陷阱特征,1／f噪声的增加归因于电应力在器件有源区诱生的界面陷阱和表面陷阱,因而,1／f噪声可以用来探测电应力对该类器件有源区的潜在损伤。     

Infrared focal plane array incorporating silicon IC processcompatible bolometer

A 128×128 element bolometer infrared image sensor using thin film titanium is proposed. The device is a monolithically integrated structure with a titanium bolometer detector located over a CMOS circuit that reads out the bolometer's signals. By employing a metallic material like titanium and refining the CMOS readout circuit, it is possible to minimize 1/f noise. It is demonstrated that the use of low 1/f noise material will help increase bias current and improve the S/N ratio. Since the fabrication process is silicon-process compatible, costs can be kept low     

Intrinsic 1/f device noise reduction and its effect on phase noisein CMOS ring oscillators

This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the oscillator's close-in phase noise. More specifically, it is shown that the 1/f³ phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1/f³ phase noise than expected. It will be shown that this can be attributed to the intrinsic 1/f noise reduction effect due to periodic on-off switching     

Device optimization for digital subthreshold logic operation

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.     

A low-noise amplifier with automatic gain control and anticlipping control in CMOS technology

A CMOS low-noise amplifier (LNA) with two variable gain ranges of 6 and 9 dB is presented. Variable gain is realized by using linearized MOS resistive circuits (MRCs) as voltage-controlled resistors. One of these resistors is located in the feedback loop of a transresistance output stage and the other is in the bias current generator of the transconductance input stage. Using compatible lateral bipolar transistors (CLBTs) in the fully differential transconductance input stage, the circuit takes advantage of the linear dependence of transconductance on bias current. The equivalent noise is 14 nV/ square root Hz and free from 1/f noise in the voice band. The circuit was integrated in a 2- mu m CMOS process and has an active area of 0.8 mm/sup 2/.<>     

A monolithically integrated three-axis accelerometer using CMOScompatible stress-sensitive differential amplifiers

In this paper, the development of a bulk-micromachined CMOS integrated three-axis accelerometer which includes analog signal conditioning circuits is presented. The accelerometer was designed to simplify the signal processing tasks by incorporating a set of circuits for three-axis signal conditioning. This approach resulted in a 25% reduction of the circuit area. Stress-sensitive differential amplifiers (SSDAs) have been used as signal transducers, because they can be conveniently formed in a small area. The sensitivity and resolution of the fabricated devices realized in 8×8 mm² die area were 192 mV/g and 0.024 g for Z-axis acceleration, and 23 mV/g and 0.23 g for X and Y axis acceleration, respectively. The electrical noise component in the analog CMOS circuits was reduced by using a chopper stabilization technique. It was observed that there is a proper chopping clock frequency range to maximize the noise reduction effect. The noise of the SSDA was found to be related with the characteristics of CMOS differential amplifiers used. Typical temperature coefficient of sensitivity was about -2000 ppm/°C, which could be reduced to -320 ppm/°C or less by selecting a proper bias condition