Simultaneous All-Optical and and nor Gates for NRZ Differential Phase-Shift-Keying Signals

A scheme for realizing all-optical logic AND and NOR gates simultaneously for nonreturn-to-zero differential phase-shift-keying signals is proposed and demonstrated based on a delayed interferometer and two semiconductor optical amplifiers. Experimental demonstration at 20 Gb/s verifies the logic integrity of this scheme. The final results are derived in the ON-OFF keying format with clear open eyes and extinction ratios over 10 dB. The proposed scheme can be expanded to realize arbitrary logic gate.     

Proposal for All-Optical Switchable or/xor Logic Gates Using Sum-Frequency Generation

All-optical logic gate based on parametric processes in periodically poled lithium niobate (PPLN) waveguides is a promising technique in future high-speed all-optical signal processing. A simple realization of switchable or/xor logic gates at 40 Gb/s is proposed and numerically demonstrated using sum-frequency generation in a PPLN waveguide. By appropriately adjusting the input signal power and choosing the waveguide length, or and xor logic gates can be obtained. The operation performance is simulated, including eye diagrams and Q-factor. The input signal powers and waveguide length are optimized, providing a theoretical basis for achieving the optimal performance for the switchable or/xor logic gates     

Solution-Processed n-Type Organic Field-Effect Transistors With High on /off Current Ratios Based on Fullerene Derivatives

Solution-processed n-type organic field-effect transistors (OFETs) based on the fullerene derivative {6}-1-(3-(2- thienylethoxycarbonyl)-propyl)-{5}-l-phenyl-[5,6]-C61 (TEPP) and phenyl-C61-butyric acid methyl ester (PCBM) in a multiring source/drain structure are reported. Devices with TEPP show high electron mobility up to 7.8 x 10^-2 cm²/Vs in the saturation regime for bottom-contact OFETs with Au S/D electrodes with a solution-processed fullerene derivative. The ON/OFF ratios reported in this letter, which are in the range of 10⁵ -10⁶, are among the highest values reported for such devices. This mobility is always higher compared to PCBM devices prepared in identical conditions. The mobility of TEPP and PCBM increased with increasing temperatures in the range of 100-300 K with activation energy of 78 and 113 meV, respectively, which suggests that the thermally activated hopping of electrons is dominant in TEPP.     

Modeling nand Flash Memories for IC Design

In this letter, we present a compact model of NAND flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simulation of NAND flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.     

Miniaturized Unconstrained on– off Pneumatic Poppet Valve—Experiment and Simulation

We present here an analysis and simulation model of an unconstrained on-off poppet valve, which includes the modeling of a piezoelectric actuator (PEA), Hertzian contact, dynamics of poppet motion, and airflow through an orifice. The flow rate generated and the input/output relationship between input frequency/flow rate and voltage/flow rate at different levels of inlet pressure were measured experimentally. Simulation models were built and verified experimentally for valves with different piezoelectric dimensions. Comparisons of simulation and experimental results showed good agreement, thus validating the proposed dynamic analysis. This model can therefore be used to understand the behavior of unconstrained on-off poppet valves. Poppet size did not have a significant effect on flow rate output. Also, the flow rate responses of different sizes of PEAs revealed that larger cross-sectional areas produced higher flow rates. Based on the experimental and simulation results, unconstrained valves were characterized as on-off valves. These findings indicate that this analytical model can be used to predict or estimate the input/output behavior of valves with different parameters.     

nand Flash Memory and Its Role in Storage Architectures

This papers reviews the increasing role of nand flash memory in storage architectures. nand flash has enjoyed a phenomenal growth rate in storage capacities as well as a steady decline in pricing during the past few years. These developments have enabled nand to enter and possibly change or displace some traditional storage architectures. However, besides cost, nand flash memory has some reliability and performance issues that will slow its adoption into all storage architectures. This paper will analyze the advantages and disadvantages of this technology and the implications to the current and possible future storage architectures. Moreover, we will analyze nand flash future density and costs trends and compare them with the traditional hard disk drive.      

On-Resistance Modulation of High Voltage GaN HEMT on Sapphire Substrate Under High Applied Voltage

The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device.     

Finite-Element Analysis of Ex Vivo and In Vivo Hepatic Cryoablation

Cryoablation is a widely used method for the treatment of nonresectable primary and metastatic liver tumors. A model that can accurately predict the size of a cryolesion may allow more effective treatment of tumor, while sparing normal liver tissue. We generated a computer model of tissue cryoablation using the finite-element method (FEM). In our model, we considered the heat transfer mechanism inside the cryoprobe and also cryoprobe surfaces so our model could incorporate the effect of heat transfer along the cryoprobe from the environment at room temperature. The modeling of the phase shift from liquid to solid was a key factor in the accurate development of this model. The model was verified initially in an ex vivo liver model. Temperature history at three locations around one cryoprobe and between two cryoprobes was measured. The comparison between the ex vivo result and the FEM modeling result at each location showed a good match, where the maximum difference was within the error range acquired in the experiment (< 5 degC). The FEM model prediction of the lesion size was within 0.7 mm of experimental results. We then validated our FEM in an in vivo experimental porcine model. We considered blood perfusion in conjunction with blood viscosity depending on temperature. The in vivo iceball size was smaller than the ex vivo iceball size due to blood perfusion as predicted in our model. The FEM results predicted this size within 0.1-mm error. The FEM model we report can accurately predict the extent of cryoablation in the liver.     

Nanocrystal Memory Cell Integration in a Stand-Alone 16-Mb nor Flash Device

We report on the full process integration of nanocrystal (NC) memory cells in a stand-alone 16-Mb NOR Flash device. The Si NCs are deposited by chemical vapor deposition on a thin tunnel oxide, whose surface is treated with a low thermal budget process, which increases NC density and minimizes oxide degradation. The device fabrication has been obtained by means of conventional Flash technology, which is integrated with the CMOS periphery with high- and low-voltage transistors and charge pump capacitors. The memory program and erase threshold voltage distributions are well separated and narrow. The voltage distribution widths are related to NC sizes and dispersion, and bigger NCs can induce a cell reliability weakness. An endurance issue is also related to the use of an oxide/nitride/oxide dielectric which acts as a charge trapping layer, causing a shift in the program/erase window and a distribution broadening during cycling.     

Optical Encryption With OCDMA Code Swapping Using All-Optical xor Logic Gate

A novel optical code-division multiple access (OCDMA) transmission system with all-optical exclusive or (xor) encryption architecture is proposed and demonstrated. This all-optical system conducts OCDMA code swapping based on xor operation. This multilayer approach eliminates radio-frequency data radiation and improves the confidentiality of the transmission system.      

Monolithically Integrated Logic nor Gate Based on GaAs/AlGaAs Three-Terminal Junctions

Room-temperature operation of a logic NOR gate is demonstrated. The NOR gate is based on three three-terminal junctions (TTJs) monolithically integrated in a modulation-doped GaAs/AlGaAs heterostructure without any external load resistance. For the logic NOR gate, one of the TTJs serves as load transistor, whereas the other two are used as inputs. Each TTJ has a 90-nm-wide channel and shows clear transistor characteristics with drain currents up to 10 muA for a drain voltage of 1 V. Furthermore, voltage amplification is demonstrated for the logic NOR-gate function.     

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

An on–off-Keying Optical Receiver With Dual Thresholds and Erasure Zone

An ON-OFF-keying optical receiver with dual thresholds and an erasure zone is proposed. This configuration can be applied to track the optimized decision level adaptively and obtain additional coding gain from forward-error correction without increasing the code rate. Our analysis shows that in both unamplified and optically preamplified receivers, the required Q value for the bit-error rate of 10^-12 can be reduced by 1.8 dB, if errors arise in burst nature and the optimized erasure zone width is around 7%-11% of the signal swing.     

The Evolving Face of Ethics in Technical and Professional Communication: Challenger to Columbia

Our view of ethics in professional and technical communication has evolved, paralleling developments throughout society. Earlier views on ethics and values have grown into a broad perspective of complex gradations with people at many levels affecting eventual practical outcomes. This newer perspective includes not only persons but social forces and organizations. The organizational culture of NASA, for example, was specifically identified by the Columbia Accident Investigation Board (CAIB) as one of the causes of faulty communication leading to a terribly tragic event. The Challenger investigations of 20 years earlier, on the other hand, focused primarily on physical events, secondarily on professional judgments, and only little on the social and cultural context of the disaster. We learn by failures but also by self-examination. As we see how ethics and values impact technical events, we understand that technological progress is ultimately a human endeavor in which reflection and judgment is as important as measurement and observation.     

A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

An on-chip high-speed two-cell Bose–Chaudhuri–Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) nor flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time–area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of nor flash memories.      

Dual Gate ZnO-Based Thin-Film Transistors Operating at 5 V: nor Gate Application

We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20-nm-thick $hbox{Al}_{2}hbox{O}_{3}$ for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at 200 $^{ circ}hbox{C}$. As characterized with single gate (SG), DG, and ground plane (GP) modes, our ZnO TFTs are well operated under 5 V. DG-mode TFT showed a field mobility of 0.38 $ hbox{cm}^{2}/hbox{V} cdot hbox{s}$, a high saturation current of 6 $muhbox{A}$, and an on/off current ratio of $sim hbox{10}^{6}$, while SG- and GP-mode TFTs showed a similar value of mobility but with lower current. Using DG and GP modes, nor gate operation was well demonstrated.      

All-Optical Processing Based on a Logic xor Gate and a Flip-Flop Memory for Packet-Switched Networks

The routing functionality by all-optically interconnecting semiconductor-based all-optical logic gates and flip-flops is demonstrated in the frame of an all-optical label swapping (AOLS) network. We experimentally show that the output of the all-optical 2-bit correlator is capable of toggling the states of the integrated flip-flop every 2.5 ns via an adaptation stage. High extinction ratios are obtained at the output of the flip-flop, which can be used to feed a high-speed wavelength converter to complete the routing functionality of the AOLS node. The potential integration of these semiconductor optical amplifier integrated Mach-Zehnder interferometer-based devices make the proposed approach a very interesting solution for future packet switched optical networks.     

A mux-based High-Performance Single-Cycle CMOS Comparator

In this brief, a new architecture for high-fan-in CMOS comparator is proposed. The architecture is based on a hierarchical two-stage comparator structure and a dynamic MUX is used instead of a comparator in the second stage of the structure. By doing so, the fast dynamic MUX significantly improves the overall delay of the high-fan-in comparators. At the same time, a novel high-performance static priority encoder is proposed to generate the control signal for the MUX. A 64-bit MUX-based comparator has been built and compared with the existing fastest single-cycle design in the study by Lam and Tsui (2006). From both the post-layout simulation and test-chip measurement results, it is shown that the performance is improved by around 28%.