Simultaneous All-Optical and and nor Gates for NRZ Differential Phase-Shift-Keying Signals

A scheme for realizing all-optical logic AND and NOR gates simultaneously for nonreturn-to-zero differential phase-shift-keying signals is proposed and demonstrated based on a delayed interferometer and two semiconductor optical amplifiers. Experimental demonstration at 20 Gb/s verifies the logic integrity of this scheme. The final results are derived in the ON-OFF keying format with clear open eyes and extinction ratios over 10 dB. The proposed scheme can be expanded to realize arbitrary logic gate.     

Proposal for All-Optical Switchable or/xor Logic Gates Using Sum-Frequency Generation

All-optical logic gate based on parametric processes in periodically poled lithium niobate (PPLN) waveguides is a promising technique in future high-speed all-optical signal processing. A simple realization of switchable or/xor logic gates at 40 Gb/s is proposed and numerically demonstrated using sum-frequency generation in a PPLN waveguide. By appropriately adjusting the input signal power and choosing the waveguide length, or and xor logic gates can be obtained. The operation performance is simulated, including eye diagrams and Q-factor. The input signal powers and waveguide length are optimized, providing a theoretical basis for achieving the optimal performance for the switchable or/xor logic gates     

Solution-Processed n-Type Organic Field-Effect Transistors With High on /off Current Ratios Based on Fullerene Derivatives

Solution-processed n-type organic field-effect transistors (OFETs) based on the fullerene derivative {6}-1-(3-(2- thienylethoxycarbonyl)-propyl)-{5}-l-phenyl-[5,6]-C61 (TEPP) and phenyl-C61-butyric acid methyl ester (PCBM) in a multiring source/drain structure are reported. Devices with TEPP show high electron mobility up to 7.8 x 10^-2 cm²/Vs in the saturation regime for bottom-contact OFETs with Au S/D electrodes with a solution-processed fullerene derivative. The ON/OFF ratios reported in this letter, which are in the range of 10⁵ -10⁶, are among the highest values reported for such devices. This mobility is always higher compared to PCBM devices prepared in identical conditions. The mobility of TEPP and PCBM increased with increasing temperatures in the range of 100-300 K with activation energy of 78 and 113 meV, respectively, which suggests that the thermally activated hopping of electrons is dominant in TEPP.     

PPLN-Based Flexible Optical Logic and Gate

All-optical flexible 20-Gb/s logic and gate based on cascaded sum- and difference-frequency generation in a periodically poled lithium niobate waveguide is proposed and experimentally demonstrated. The theoretical analyses further indicate that 40-, 80-, and 160-Gb/s ultrahigh-speed logic and operations can potentially be performed. Moreover, it is expected that the and output can be tuned in a wide wavelength range (67 nm) with slight fluctuation of the Q-factor and extinction ratio.     

Modeling nand Flash Memories for IC Design

In this letter, we present a compact model of NAND flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simulation of NAND flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.     

Miniaturized Unconstrained on– off Pneumatic Poppet Valve—Experiment and Simulation

We present here an analysis and simulation model of an unconstrained on-off poppet valve, which includes the modeling of a piezoelectric actuator (PEA), Hertzian contact, dynamics of poppet motion, and airflow through an orifice. The flow rate generated and the input/output relationship between input frequency/flow rate and voltage/flow rate at different levels of inlet pressure were measured experimentally. Simulation models were built and verified experimentally for valves with different piezoelectric dimensions. Comparisons of simulation and experimental results showed good agreement, thus validating the proposed dynamic analysis. This model can therefore be used to understand the behavior of unconstrained on-off poppet valves. Poppet size did not have a significant effect on flow rate output. Also, the flow rate responses of different sizes of PEAs revealed that larger cross-sectional areas produced higher flow rates. Based on the experimental and simulation results, unconstrained valves were characterized as on-off valves. These findings indicate that this analytical model can be used to predict or estimate the input/output behavior of valves with different parameters.     

nand Flash Memory and Its Role in Storage Architectures

This papers reviews the increasing role of nand flash memory in storage architectures. nand flash has enjoyed a phenomenal growth rate in storage capacities as well as a steady decline in pricing during the past few years. These developments have enabled nand to enter and possibly change or displace some traditional storage architectures. However, besides cost, nand flash memory has some reliability and performance issues that will slow its adoption into all storage architectures. This paper will analyze the advantages and disadvantages of this technology and the implications to the current and possible future storage architectures. Moreover, we will analyze nand flash future density and costs trends and compare them with the traditional hard disk drive.      

On-Resistance Modulation of High Voltage GaN HEMT on Sapphire Substrate Under High Applied Voltage

The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device.     

2008 Scott Helt Memorial Award for the Best Paper Published in the IEEE Transactions on Broadcasting

Th 2008 Scott Helt Memorial Award was awarded to Gunther May and Michael Kornfeld for their paper, "DVB-H and IP-Datacast - Broadcast to Handheld Devices," published in the March 2007 issue.     

A New Architecture for High-Density High-Performance SGT nor Flash Memory

In order to overcome the limitation of a conventional NOR flash memory, we propose a new architecture using a surrounding gate transistor (SGT) NOR flash memory to realize both Fowler-Nordheim (FN)-tunneling program and high-speed random access read operation. The SGT NOR flash memory cell has a 3D structure, in which the source, gate and drain are vertically stacked. The gate surrounds a silicon pillar. The source line of a diffusion layer and the metal bit line (BL) are wired to the bottom and the top of the silicon pillar, respectively. The BL and SL are arranged in the same column direction and the gate line is wired in the row direction. This structure enables the same voltage to be simultaneously applied to both the SL and BL of the same column. Therefore, the SGT NOR flash memory cell can be written and erased by the FN-tunneling mechanism. In read operation, the metal common SL is connected with the SL every 16 memory cells to reduce the resistance of the SL. As a result, a read current is improved and a high-speed read operation can be achieved. Furthermore, the SGT NOR flash memory adapts to 50-nm node to obtain a compact cell area of 6.6 and a large read current of 72 muA; the cell area can be reduced by 54% and a read current increase by 227% compared to the conventional NOR flash memory. Owing to high-density and high-speed features, the SGT NOR flash memory is a promising structure for the future high-density and high-performance flash memory.     

Approximation for a Sum of on-off Lognormal Processes With Wireless Applications

In this paper, a lognormal approximation is proposed for the sum of lognormal processes weighted by binary processes. The analytical approach moves from the method early proposed by Wilkinson for approximating first-order statistics of a sum of lognormal components, and extends to incorporate second-order statistics and the presence of both time-correlated random binary weights and cross-correlated lognormal components in moments' matching. Since the sum of weighted lognormal processes models the signal-to-interference-plus-noise ratio (SINR) of wireless systems, the method can be applied to evaluate in an effective and accurate way the outage occurrence rate and outage duration for different wireless systems of practical interest. In a frequency-reuse-based cellular system, the method is applied for various propagation scenarios, characterized by different shadowing correlation decay distances and correlations among shadowing components. A further case of relevant interest is related to power-controlled wideband wireless systems, where the random weights are binary random variables denoting the activity status of each interfering source. Finally, simulation results are used to confirm the validity of the analysis.     

Long Term Study of Peer Behavior in the kad DHT

Distributed hash tables (DHTs) have been actively studied in literature and many different proposals have been made on how to organize peers in a DHT. However, very few DHTs have been implemented in real systems and deployed on a large scale. One exception is KAD, a DHT based on Kademlia, which is part of eDonkey, a peer-to-peer file sharing system with several million simultaneous users. We have been crawling a representative subset of KAD every five minutes for six months and obtained information about geographical distribution of peers, session times, daily usage, and peer lifetime. We have found that session times are Weibull distributed and we show how this information can be exploited to make the publishing mechanism much more efficient. Peers are identified by the so-called KAD ID, which up to now was assumed to be persistent. However, we observed that a fraction of peers changes their KAD ID as frequently as once a session. This change of KAD IDs makes it difficult to characterize end-user behavior. For this reason we have been crawling the entire KAD network once a day for more than a year to track end-users with static IP addresses, which allows us to estimate end-user lifetime and the fraction of end-users changing their KAD ID.     

Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime

A smart repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pattern on the wires and thus the effective capacitive load. This is achieved by partitioning the driver into main and assistant drivers; for a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. In a UMC 0.18-mum technology the potential energy saving is around 10% and the reduction in jitter 20%, in comparison to a traditional repeater for typical global wire lengths. It is also shown that the average energy saving for nanometer technologies is in the range of 20% to 25%. The driver architecture exploits the fact that as feature sizes decrease, the capacitive load per transistor shrinks, whereas global wire loads remain relatively unchanged. Hence, the smaller the technology, the greater the potential saving.     

Finite-Element Analysis of Ex Vivo and In Vivo Hepatic Cryoablation

Cryoablation is a widely used method for the treatment of nonresectable primary and metastatic liver tumors. A model that can accurately predict the size of a cryolesion may allow more effective treatment of tumor, while sparing normal liver tissue. We generated a computer model of tissue cryoablation using the finite-element method (FEM). In our model, we considered the heat transfer mechanism inside the cryoprobe and also cryoprobe surfaces so our model could incorporate the effect of heat transfer along the cryoprobe from the environment at room temperature. The modeling of the phase shift from liquid to solid was a key factor in the accurate development of this model. The model was verified initially in an ex vivo liver model. Temperature history at three locations around one cryoprobe and between two cryoprobes was measured. The comparison between the ex vivo result and the FEM modeling result at each location showed a good match, where the maximum difference was within the error range acquired in the experiment (< 5 degC). The FEM model prediction of the lesion size was within 0.7 mm of experimental results. We then validated our FEM in an in vivo experimental porcine model. We considered blood perfusion in conjunction with blood viscosity depending on temperature. The in vivo iceball size was smaller than the ex vivo iceball size due to blood perfusion as predicted in our model. The FEM results predicted this size within 0.1-mm error. The FEM model we report can accurately predict the extent of cryoablation in the liver.     

Nanocrystal Memory Cell Integration in a Stand-Alone 16-Mb nor Flash Device

We report on the full process integration of nanocrystal (NC) memory cells in a stand-alone 16-Mb NOR Flash device. The Si NCs are deposited by chemical vapor deposition on a thin tunnel oxide, whose surface is treated with a low thermal budget process, which increases NC density and minimizes oxide degradation. The device fabrication has been obtained by means of conventional Flash technology, which is integrated with the CMOS periphery with high- and low-voltage transistors and charge pump capacitors. The memory program and erase threshold voltage distributions are well separated and narrow. The voltage distribution widths are related to NC sizes and dispersion, and bigger NCs can induce a cell reliability weakness. An endurance issue is also related to the use of an oxide/nitride/oxide dielectric which acts as a charge trapping layer, causing a shift in the program/erase window and a distribution broadening during cycling.