Effect of nitridation on the reliability of thick gate oxides

In this work the effect of nitridation on the reliability of thick (60 nm) gate oxides used in discrete power MOSFETs is investigated. Nitridation was carried out by post-oxidation anneal in N₂O at 1000 °C. Secondary ion mass spectroscopy characterization did show that the nitrogen resulting from N₂O nitridation piles up in the oxide at the Si–SiO₂ interface regardless of nitridation time. The results obtained show improved breakdown field (E_bd), and charge-to-breakdown (Q_bd) characteristics for nitrided thick oxides. Also, lower mid-bandgap interface trap density (D_it) was observed in the case of nitrided oxides. Key conclusion from this experiment is that nitridation of thick (>50 nm) gate oxide performed to suppress boron penetration into the MOSFET channel region is not having an adverse effect on its electrical characteristics.     

A new algorithm for transforming exponential current ramp breakdown distributions into constant current TDDB space, and the implications for gate oxide QBD measurement methods

Charge-to-breakdown (Q_BD) is one of the manufacturing parameters that is used as a measure of oxide quality. In this work the influence of the measurement conditions on Q_BD is examined, as well as the relationship between Q_BD and oxide thickness. Using oxides ranging from 45 to 80 Å, two Q_BD measurement methods are employed: constant current stress (CCS) and an exponential current ramp (ECR). A variety of current densities (for the constant current stress) and step durations (for the exponential current ramp) are studied. It is shown that not only does Q_BD depend on oxide thickness, but that Q_BD depends strongly on the measurement conditions, and that, depending on the test conditions, Q_BD can increase or decrease as the oxide thickness decreases. It is also shown that there is a strong agreement between the Q_BD measured with a constant current stress and the Q_BD measured with an exponential current ramp. Finally, an algorithm is proposed for transforming the Q_BD distribution obtained from a series of exponential current ramps into the Q_BD and/or t_BD domains of constant current stressing.     

Oxide reliability: influence of interface roughness, structure layout, and depletion layer formation

The charge to breakdown Q_bd and the breakdown voltage V_bd distributions obtained on 7.5 and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms are discussed in terms of the GOX interface roughness and the depletion effects during the stress. The observed influence of the interface roughness on the GOX properties seems to be very sensitive to the gate polarity during the stress or the injection direction of electrons. Especially the roughness of the interface through which electrons are injected into the gate oxide influences the oxide reliability. The effect of the interface roughness turned out to depend strongly on the test acceleration level. A possibility of masking of the roughness (reduction of the “effective roughness”) of the GOX/Si interface as a result of strong depletion at higher accelerations is discussed.     

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p+ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C–V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p+ poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

薄栅介质层可靠性与陷阱统计分析

本文以高电场(＞11.8MV/cm)恒电流TDDB为手段研究了厚度为7.6、10.3、12.5、14.5nm薄氧化层的击穿统计特性.实验分析表明在加速失效实验中测量击穿电量Q_bd的同时,还可以测量击穿时的栅电压增量ΔV_bd.因为ΔV_bd的统计分布反映了栅介质层中带电陷阱的数量及其位置分布,可以表征栅介质层的质量和均匀性.此外由Q_bd和ΔV_bd能够较合理地计算临界陷阱密度N_bd.实验结果表明本征击穿时N_bd与测试条件无关而随工艺和介质层厚度变化.同样厚度时N_bd反映不同工艺生成的介质质量.陷阱生成的随机性使N_bd随栅介质厚度减小而下降.氧化层厚度约10nm时N_bd达到氧化层分子密度的1%发生击穿(10²⁰cm^-3).N_bd的物理意义清楚,不象Q_bd随测试应力条件变化,是薄栅介质层可靠性的较好的定量指标.     

Ultra-thin oxide reliability: searching for the thickness scaling limit

The degradation and breakdown of ultra-thin oxide layers are discussed. Physical insights are provided for various experimental observations such as stress-induced leakage current, soft breakdown and the polarity gap for Q_BD. The cumulative effect of a wider statistical spread and stronger temperature acceleration for ultra-thin oxides is shown to lead to insufficient reliability below 2.5 nm.     

Depassivation of latent plasma damage in pMOS devices

While plasma-induced charging damage has been widely studied in recent years, much of the work has concentrated upon the impact on n-channel MOSFET reliability [1–6]. This work focuses the impact of plasma damage on pMOS devices from the viewpoint of oxide trapped charge and interface states with the experimental featuring two parameters Q_p and ΔN_p, linked respectively to the oxide charge and the interface state density. This experimental method is valid for pMOS devices in two different technologies and permits to fully compare devices with different oxide thickness. Furthermore, we demonstrate that, for a given antenna, the plasma damage roughly has the same net impact on transistor characteristics, regardless of oxide thickness.     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

Depassivation of latent plasma damage in devices

While plasma-induced charging damage has been widely studied in recent years, much of the work has concentrated upon the impact on n-channel MOSFET reliability [1–6]. This work focuses the impact of plasma damage on pMOS devices from the viewpoint of oxide trapped charge and interface states with the experimental featuring two parameters Q_p and ΔN_p, linked respectively to the oxide charge and the interface state density. This experimental method is valid for pMOS devices in two different technologies and permits to fully compare devices with different oxide thickness. Furthermore, we demonstrate that, for a given antenna, the plasma damage roughly has the same net impact on transistor characteristics, regardless of oxide thickness.     

The performance and reliability of PMOSFET's with ultrathin siliconnitride/oxide stacked gate dielectrics with nitrided Si-SiO2interfaces prepared by remote plasma enhanced CVD and post-depositionrapid thermal annealing

Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si₃N₄ onto oxides. Compared to PMOSFET's with heavily doped p⁺-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys     

Defect centroid,patial distribution,and areal density in process-induced radiation-damaged IGFETs with gate insulators grown at 1000 and 800° C

IGFET devices were fabricated with “dry” gate oxides grown at 1000 and 800° C in the thickness range 5–50 nm. They were then exposed in an electrically unbiased state to Al K_α x-ray (1.49 keV) radiation to simulate process-induced ionizing radiation exposure. Gate oxide defects were measured before and after irradiation using optically assisted electron injection. Following irradiation and injection, the measured voltage shifts indicate that radiation-induced “extrinsic” defects are localized near, but not exactly at, the Si/SiO₂ interface.ΔV _T is found to be linear int _ox for oxide thicknesses where the top electrode resides above the defect region, and quadratic int _ox for thicknesses where the top electrode encroaches upon the defect region. For very thin oxides,ΔV _T is observed to approach zero. Application of a defect distribution model based on this behavior reveals that the oxidation temperature does not influence the distribution of radiation-induced defects, but does influence their concentration; with the 800° C oxides always containing more defects than the 1000° C oxides. A gate oxide thickness regime of less than 5-6 nm is identified in which radiation-induced threshold voltage shifts are observed to approach zero.     

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N₂O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-breakdown and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra thin oxides in charge-to-breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between nand p-MOSFETs. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N₂O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (T_ox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with T_ox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

RTP annealings for high-quality LPCVD interpolysilicon dielectric layers

Deposited instead of thermally grown oxides were studied to form high-quality interpolysilicon dielectric layers for embedded non-volatile memory application. It was found that by optimizing the texture and morphology of the polysilicon layers and by optimizing the post-dielectric deposition-anneal, very high-quality dielectric layers can be obtained. In this paper it is shown that for deposited interpolysilicon oxides rapid thermal annealing leads to improved electrical characteristics, like high charge to breakdown (Q_bd≈20 C/cm²), lower leakage currents and decreased charge trapping during stress, depending on the RTP anneal ambient. Three annealing ambients are compared: N₂, O₂ and N₂O. Annealing in N₂O ambient is shown to be superior to the other annealings.     

采用AlN/SiNx钝化的高性能AlGaN/GaN HEMTs

两种不同的钝化层结构被应用到势垒层厚度为12 nm的AlGa/GaN 高电子迁移率场效应晶体管中。首先采用等离子增强原子层沉积(PEALD)技术生长5 nm的AlN薄膜,然后再覆盖50 nm的等离子增强化学气相淀积(PECVD)生长的SiNx。相比于传统的SiNx钝化,AlN钝化层的插入更有效地抑制了电流崩塌效应,同时获得了小的亚阈值斜率(SS)。AlN钝化层的插入增大了器件的射频跨导从而获得了较高的截止频率。另外,通过变温直流特性测试发现,AlN/SiNx钝化的器件在高温时饱和电流和最大跨导的衰退相对于仅采用SiNx钝化的器件都要小,表明AlN钝化层的插入改善了器件的高温稳定性。     

Stress polarity dependence of the activation energy intime-dependent dielectric breakdown of thin gate oxides

Stress polarity dependence of the activation energies in the two time dependent dielectric breakdown measurements, the constant-current injection (Q_bd testing) and the constant-voltage stressing (t _bd testing) are investigated for gate oxides with the thickness ranging from 10 to 4 nm. A remarkable polarity dependence of the activation energies appears in the t_bd testing when the oxide thickness decreases. This phenomenon is found to be due to a characteristic temperature dependence of the gate current density during the whole t_bd testing period for thinner oxides, which is considered as a result from the temperature dependence of the electron trapping process during the stressing     

Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, t_ox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V_th and of linear drain current I_dlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of V_th and I_dlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO₂/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.