Optimum design for minimum on-resistance of low voltage trench power MOSFET

An optimum trench width for the minimum on-resistance of a trench MOSFET (T-MOS) is determined analytically with the resistance contribution from the accumulation layer taken into account. Inclusion of the accumulation resistance is shown to be indispensable to the on-resistance of the T-MOS especially for a relatively large value of the trench width. The analytical results show a fair agreement with the numerical simulations using ATLAS.     

Design of 700 V triple RESURF nLDMOS with low on-resistance

A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ·cm~2 is designed.Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region,the P-type layer of a triple RESURF nLDMOS is located within it.The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30%lower specific on-resistance at the same given breakdown voltage of 700 V.Detailed research of the influences of various parameters on breakdown voltage,specific on-resistance,as well as process tolerance is involved.The results may provide guiding principles for the design of triple RESURF nLDMOS.     

Design of 700 V triple RESURF nLDMOS with low on-resistance

A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ·cm² is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.     

低比导通电阻P埋层SOI双介质槽MOSFET

提出了一种带P型埋层的新型SOI双介质槽MOSFET.通过在SOI层底部引入P型埋层作为补偿,在耐压优化情况下增加漂移区的浓度,降低了比导通电阻.MEDICI TCAD仿真结果表明:在281 V击穿电压下,该结构的比导通电阻为4.6 mΩ·cm2,与不带P型埋层的结构相比,在达到同样耐压的情况下,比导通电阻降低了19％.     

DC-DC转换器中功率沟槽MOSFET的优化设计

利用工艺和器件模拟软件TSUPREM-4和MEDICI,研究了工艺参数对DC-DC转换器中的功率沟槽MOSFET的通态电阻Ron、栅-漏电容Cgd的影响以及栅-漏电荷Qgd在开关过程中的变化,指出了在设计和工艺上减小通态电阻Ron和栅-漏电容Cgd,提高器件综合性能的途径。     

具有L型低阻导电通道的介质场增强SOI LDMOS

A low specific on-resistance（R on;sp/ SOI NBL TLDMOS（silicon-on-insulator trench LDMOS with an N buried layer） is proposed. It has three features： a thin N buried layer（NBL） on the interface of the SOI layer/buried oxide（BOX） layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on;sp. Second, in the y-direction, the BOX＇s electric field（E-field） strength is increased to 154 V/ m from48 V/ m of the SOI Trench Gate LDMOS（SOI TG LDMOS） owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage（BV）, but also reduces the cell pitch and R on;sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on;sp by 80% at the same BV.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

一种低导通电阻低转折电压的双通道分段阳极横向IGBT

A dual conduction paths segmented anode lateral insulated-gate bipolar transistor （DSA-LIGBT） which uses triple reduced surface field （RESURF） technology is proposed. Due to the hybrid structures of triple RESURF LDMOS （T-LDMOS） and traditional LIGBT, firstly, a wide p-type anode is beneficial to the small shift voltage （VST） and low specific on-resistance （Ron,sp） when the anode voltage （VA） is larger than VST. Secondly, a wide n-type anode and triple RESURF technology are used to get a low Ron,sp when VA is less than VST. Meanwhile, it can accelerate the extraction of electrons, which brings a low turn-off time （Toff）. Experimental results show that： VST is only 0.9 V, Ron,sp （Ron × Area） are 11.7 and 3.6 Ω · mm^2 when anode voltage VA equals 0.9 and 3 V, respectively, the breakdown voltage reaches to 800 V and Toff is only 450 ns.     

新型具有低比导通电阻的多超结功率器件结构

提出一种新型多超结LDMOS功率器件,通过在横向和和纵向P柱区与N柱区之间的相互作用降低器件的导通电阻。在这一结构中,多层超结通过相互反向排列而形成,相比于常规超结的二维耗尽,MSJ由于纵向电场调制的作用形成三维耗尽,并且由于深漏的存在,电流分布更好,在各项条件的作用下,漂移区的掺杂浓度得到了提高,降低了器件导通电阻。底层超结的电场屏蔽效应使得该器件达到电荷平衡,由于衬底辅助耗尽效应效应产生的漏区高电场降低了,在漂移区产生一个均匀分布的电场并且获得高击穿电压。通过数值模拟仿真验证表明：在维持高击穿电压的情况下,长12微米的MSJ功率器件的导通电阻相比于同样大小的常规器件降低了42%。     

Design of 100‐V Super‐Junction Trench Power MOSFET with Low On‐Resistance

Power metal‐oxide semiconductor field‐effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double‐diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on‐state resistance and breakdown voltage. To overcome the tradeoff relationship, a super‐junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on‐state resistance of 1.2 mΩ‐cm² at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.     

Simulation and Fabrication Studies of Semi‐superjunction Trench Power MOSFETs by RSO Process with Silicon Nitride Layer

In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi‐superjunction (semi‐SJ) trench double‐diffused MOSFET (TDMOS). In this new process, the thick single insulation layer (SiO₂) of a conventional device is replaced by a multilayered insulator (SiO₂/SiN_x/TEOS) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on‐resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on‐resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on‐resistance are 108 V and 1.1 mΩcm², respectively.     

A charge sheet model for MOSFETs with an abrupt retrograde channel: Part II. Charges and intrinsic capacitances

The 16 intrinsic capacitance components related to the gate, source, drain and depletion charges are examined for MOSFETs with an ideally abrupt retrograde doping profile in the channel, based on the analytical solutions for the drain current and body charge in the preceding paper. Though lengthy and complex in their final mathematical expressions, analytical solutions for the capacitances can be obtained. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations. The inclusion of an intrinsic surface layer in the channel merely causes a simple voltage shift for the capacitances that are not associated with the depletion charge or body bias, similarly to the variation of the drain current shown in the preceding paper. For the capacitances that are related to the depletion charge or body bias, there is not only a parallel voltage shift with an amount commensurate to the shift in drain current as well as in the other capacitances, but also a decrease in their values. This decrease depends on the thickness of the intrinsic surface layer and it amounts to 25% for a surface layer of 30 nm thickness.     

带电平位移电路的H桥高端功率管栅极驱动电路

提出了一种带高压电平位移电路的H桥高端功率管栅极驱动电路.电平位移电路采用脉冲下拉方式实现高压电平位移,与一般的方波下拉方式相比,有效地减小了电路的功耗.分析了脉冲下拉方式电平位移电路的工作原理与实现方式,以此为基础,设计了H桥高端驱动电路.基于5μm高压BCD工艺,采用Spectres进行电路仿真,完成了电路版图设计和流片测试.结果显示,设计的高端驱动电路能很好地实现高端功率管栅极电位的悬浮抬升.     

一种高速低尖峰电流功率管驱动器电路的设计

利用电荷泵自举原理,提出一种新颖的CMOS驱动电路。该电路在输入信号未进行开关操作时对电容充电,在开关操作发生时,由电荷泵电容和电源一起向负载电容充放电,从而可在不影响充放电时间的前提下降低电源对负载电容的充放电尖峰电流,减小电源噪声。该电路特别适合用来驱动采用高k介质或深槽隔离工艺的功率集成电路,可同时降低上升/下降沿时间和电源尖峰电流,并大幅减小芯片面积。采用中芯国际0.35μm标准CMOS工艺进行流片,测试结果表明,该电路可同时降低负载电容充放电尖峰电流与上升/下降沿时间。     

3.3 kV 4H-SiC DMOSFET with a source-contacted dummy gate for high-frequency applications

In this paper,a 4H-SiC DMOSFET with a source-contacted dummy gate(DG-MOSFET)is proposed and analyzed through Sentaurus TCAD and PSIM simulations.The source-contacted MOS structure forms fewer depletion regions than the PN junction.Therefore,the overlapping region between the gate and the drain can be significantly reduced while limiting RON degradation.As a result,the DG-MOSFET offers an improved high-frequency figure of merit(HF-FOM)over the conventional DMOSFET(C-MOSFET)and central-implant MOSFET(CI-MOSFET).The HF-FOM(RON×QGD)of the DG-MOSFET was improved by 59.2％and 22.2％compared with those of the C-MOSFET and CI-MOSFET,respectively.In a double-pulse test,the DG-MOSFET could save total power losses of 53.4％and 5.51％,respectively.Moreover,in a power circuit simulation,the switching power loss was reduced by 61.9％and 12.7％in a buck converter and 61％and 9.6％in a boost converter.