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1.
In many signal processing situations, the desired (ideal) magnitude response of the filter is a rational function:
(a digital integrator). The requirements of a linear phase response and guaranteed stable performance limit the design to a finite impulse response (FIR) structure. In many applications we require the FIR filter to yield a highly accurate magnitude response for a narrow band of frequencies with maximal flatness at an arbitrary frequency
0 in the spectrum (0, ). No techniques for meeting such requirements with respect to approximation of
are known in the literature. This paper suggests a design by which the linear phase magnitude response
can be approximated by an FIR configuration giving a maximally flat (in the Butterworth sense) response at an arbitrary frequency 0, 0<0<*. A technique to compute exact weights for the design has also been given. 相似文献
2.
In this paper we investigate new Fourier series with respect to orthonormal families of directed cycles
, which occur in the graph of a recurrent stochastic matrixP. Specifically, it is proved thatP may be approximated in a suitable Hilbert space by the Fourier series
. This approach provides a proof in terms of Hilbert space of the cycle decomposition formula for finite stochastic matricesP. 相似文献
3.
Camillo Melzi 《Circuits, Systems, and Signal Processing》1997,16(4):405-414
The aim of this paper is to give an explicit computation for the potential generated by a dipole on a hexagonal grid. Such a computation will be expressed as the Fourier transform of a distribution on the bidimensional torus
. 相似文献
4.
In this paper we investigate -bit serial addition in the context of feed-forward linear threshold gate based networks. We show that twon-bit operands can be added in
overall delay with a feed-forward network constructed with
linear threshold gates and
latches. The maximum weight value is
and the maximum fan-in is
. We also investigate the implications our scheme have to the performance and the cost under small weights and small fan-in requirements. We deduce that if the weight values are to be limited by a constantW, twon-bit operands can be added in
overall delay with a feed-forward network that has the implementation cost [logW]+1, in terms of linear threshold gates,
in terms of latches and a maximum fan-in of 3[logW]+1. We also prove that, if the fan-in values are to be limited by a constantF+1, twon-bit operands can be added in
overall delay with a feed-forward network that has the implementation cost
, in terms of linear threshold gates,
in terms of latches, and a maximum weight value of
. An asymptotic bound of
is derived for the addition overall delay in the case that the weight values have to be linearly bounded, i.e., in the order ofO(n). The implementation cost in this case is in the order ofO(logn), in terms of linear threshold gates, and in the order ofO(log2
n), in terms of latches. The maximum fan-in is in the order ofO(logn). Finally, a partition technique, that substantially reduces the overall cost of the implementation for all the schemes in terms of delay, latches, weights, and fan-in with some few additional threshold gates, is also presented. 相似文献
5.
Constant-round zero-knowledge proof systems for every language in
are presented, assuming the existence of a collection of claw-free functions. In particular, it follows that such proof systems exist assuming the intractability of either the Discrete Logarithm Problem or the Factoring Problem for Blum integers. 相似文献
6.
The ability of a parallel algorithm to make efficient use of increasing computational resources is known as its scalability. In this paper, we develop four parallel algorithms for the 2-dimensional Discrete Wavelet Transform algorithm (2-D DWT), and derive their scalability properties on Mesh and Hypercube interconnection networks. We consider two versions of the 2-D DWT algorithm, known as the Standard (S) and Non-standard (NS) forms, mapped onto P processors under two data partitioning schemes, namely checkerboard (CP) and stripped (SP) partitioning. The two checkerboard partitioned algorithms
(Non-standard form, NS-CP), and as
(Standard form, S-CP); while on the store-and-forward-routed (SF-routed) Mesh and Hypercube they are scalable as
(NS-CP), and as
(S-CP), respectively, where M
2 is the number of elements in the input matrix, and (0,1) is a parameter relating M to the number of desired octaves J as
. On the CT-routed Hypercube, scalability of the NS-form algorithms shows similar behavior as on the CT-routed Mesh. The Standard form algorithm with stripped partitioning (S-SP) is scalable on the CT-routed Hypercube as M
2 = (P
2), and it is unscalable on the CT-routed Mesh. Although asymptotically the stripped partitioned algorithm S-SP on the CT-routed Hypercube would appear to be inferior to its checkerboard counterpart S-CP, detailed analysis based on the proportionality constants of the isoefficiency function shows that S-SP is actually more efficient than S-CP over a realistic range of machine and problem sizes. A milder form of this result holds on the CT- and SF-routed Mesh, where S-SP would, asymptotically, appear to be altogether unscalable. 相似文献
7.
Maria Alessandra Fasoli 《Multidimensional Systems and Signal Processing》1998,9(3):291-306
Let K be a field, k and n positive integers and let
matrices with coefficients in K. For any function
there exists a unique solution
of the system of difference equations
defined by the matrix-k-tuple
such that
. The system
is called finite-memory system iff for every function g with finite support the values
are 0 for sufficiently big
. In the case
, these systems and the corresponding matrix-k-tuples have been studied in bis, fm, fmv, fv1, fv, fz. In this paper I generalize these results to an arbitrary positive integer k and to an arbitrary field K. 相似文献
8.
A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its
value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of
; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At
, the measured
is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications. 相似文献
9.
Bruce D. Calvert 《Circuits, Systems, and Signal Processing》1999,18(3):241-267
We study solutions of the linear system in a saturated mode
We show that a trajectory is in a constant face of the cubeD
n
on some interval (0,d]. We answer a question about comparing the two systems: (M) and
. As , limits ofv corresponding to asymptotically stable equilibrium points of (H) are asymptotically stable equilibrium points of (M), and the converse is also true. We study the assumptions to see which are required and which may be weakened. 相似文献
10.
A 5.8 GHz Low Noise Amplifier for Wireless LAN Applications in Silicon Bipolar Technology 总被引:1,自引:0,他引:1
Gerd Schuppener Mehran Mokhtari Boris Kerzar 《Analog Integrated Circuits and Signal Processing》2001,27(1-2):129-136
A monolithic integrated low-noise amplifier for operation in the 5.8-GHzband is described. Two different versions have been implemented where the biasing wasadapted to allow operation over a different range of supply voltage. At 5-V, theamplifiers gain is about 17-dB, with a noise figure of 4.2-dB and 1-dB compressionpoint at –15-dBm input power. The circuits have been designed utilizing a0.6-micron silicon bipolar production technology, featuring npn transistors with
and
of about20-GHz. 相似文献
11.
Mohammed Ahmed Ghouse 《The Journal of VLSI Signal Processing》1993,5(1):57-74
New algorithms for the DFT and the 2-dimensional DFT are presented. The DFT and the 2-dimensional DFT matrices can be expressed as the Kronecker product of DFT matrices of smaller dimension. These algorithms are synthesized by combining the efficient factorization of the Kronecker product of matrices with the highly hardware efficient recursive implementation of the smaller DFT matrices, to yield these algorithms. The architectures of the processors implementing these algorithms consist of 2-dimensional grid of processing elements, have temporal and spatial locality of connections. For computing the DFT of sizeN or for the 2D DFT of sizeN=N
1 byN
1, these algorithms require 2N multipliers and adders, take approximately
computational steps for computing a transform vector, and take approximately
computation steps between the computation of two successive transform vectors. 相似文献
12.
A novel figure of merit to describe the bandwidth power efficiency of CMOS transconductors—
is proposed and optimized for cross-coupled differential pair transconductor structures. The optimization is done in two different ways: univariable unconstrained and multivariable constrained. It is revealed that not only dc biases but also ac input phases can affect the bandwidth power efficiency of the transconductor. The bias voltages which can lead to best
ratio at different ac phase combinations are obtained and presented in the article. HSPICE simulations are conducted to verify the theoretical predictions. On the basis of the cross-coupled differential pair transconductor, a biquadratic transconductor-C filter configuration is implemented. The frequency vs. power characteristic of the filter is studied for both optimally- and non-optimally-biased transconductor. It is shown that the
optimization of the transconductor structure can result in performance improvement of the transconductor-C filter. The deviation of the optimal bias condition between the transconductor alone and the transconductor-C filter due to the inclusion of peripheray circuitries in the filter is discussed in the article. 相似文献
13.
Orientation dependent etching of photolithographically patterned
GaP was investigated using solutions of HCl:CH3COOH:H2O2. The pattern was prepared using standard ultraviolet lithography and was a two-dimensional grid with an 18 μm repeat, consisting
of 15 μm squares separated by 3 μm spaces. The mask sides were aligned along the
and
directions. Under appropriate etching conditions, high quality arrays of pyramids were prepared. These pyramids were defined
by
,
and
facets. It was shown that the etching process depended on the degree of solution aging after initial mixing. For a freshly
prepared solution, the etching rate showed an inverse dependence on time. For short etching times (below 5 min), an intermediate
etching profile was followed, while for long times (greater than 5 min) etching was kinetically controlled. We demonstrated
that controlled etching at extremely low rates (0.1–0.5 μm/min) is feasible with this new approach. 相似文献
14.
The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor
and
values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper. 相似文献
15.
Organometallic vapor phase epitaxial growth of GaAs on 320 nm high mesas was used to study the dependence of lateral growth
upon the substrate misorientation from (100) and the mesa wall orientation on the substrate. GaAs (100) substrates were misoriented
by 3° toward eight major crystallographic directions, consisting of the four nearest [111] and [110] directions. The mesa
sidewalls were oriented either parallel to the 〈011〉 and 〈01
〉 directions or rotated by 45° to be parallel to the 〈001〉 and 〈010〉 directions. GaAs films were grown with TMGa and TBA at
T=575°C. The lateral growth rates were up to 25 times higher than the vertical growth rate of 1.3 μm/hour. Optical microscopy
and atomic force microscopy (AFM) showed that under the given growth conditions lateral growth off mesa sidewalls is most
rapid in the 〈011〉 and/or 〈0
〉 directions and less in the perpendicular 〈01
〉 and 〈0
1〉 directions (lateral growth anisotropy). By raising the temperature to 625°C lateral growth in the 〈01
〉 -〈0
1〉 directions increased while it remained almost constant in the 〈011〉 -〈0
〉 directions. Published results show that the partial pressure of As also affects lateral growth. Differences in the lateral
growth rates in the 〈011〉 and its opposite 〈0
〉 directions result from substrate misorientation but not from the orientation of the mesa walls on the substrate. Anisotropic
lateral growth rates in different crystallographic directions appear to be caused by both, (1) 1-dimensional Ga diffusion
defined by surface reconstruction, and (2) a relatively low energy barrier to atoms flowing over high-to-low terrace steps.
A lateral growth model is proposed that describes anisotropic lateral growth at mesa sidewalls in terms of growth conditions
and substrate misorientations. The model also explains the difference in the preferential lateral growth directions between
MBE and OMVPE. 相似文献
16.
Yuyu Chang John Choma Jr. Jack Wills 《Analog Integrated Circuits and Signal Processing》2001,28(1):43-52
A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two
-enhancement techniques are utilized to circumvent the low
characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of
tuning, facilitating the design of the automatic tuning circuitry. The stability and the tuning scheme of the filter are also discussed. Simulations using 0.6 m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 9.5 dB noise figure, and –20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW. 相似文献
17.
Masakazu Katsuno Noboru Ohtani Tatsuo Fujimoto Hirokatsu Yashiro 《Journal of Electronic Materials》2005,34(1):91-95
The effect of off-orientation growth has been investigated in terms of stacking fault formation during physical vapor transport
(PVT) growth of silicon carbide (SiC) single crystals on the (11
0) seed crystal surface. Occurrence of stacking fault formation is largely dependent on the direction of off-orientation,
and basal plane stacking fault density is significantly reduced by growing the crystals on a (11
0) seed crystal off-oriented toward 〈0001〉. The density of the basal plane stacking faults rapidly decreases from 100–150
cm−1 to ∼10 cm−1 as the degree of off-orientation is increased from 0 to 10 deg. The results are interpreted in the framework of microscopic
facet formation during PVT growth, and the introduction of off-orientation of seed crystal is assumed to prevent (01
0) and (10
0) microfacet formation on the (11
0) growing surface through modification of the surface growth kinetics and to suppress the stacking fault formation.
An erratum to this article is available at . 相似文献
18.
Interfacial reactions of Y and Er thin films on both (111)Si and (001)Si have been studied by transmission electron microscopy
(TEM). Epitaxial rare-earth (RE) silicide films were grown on (111)Si. Planar defects, identified to be stacking faults on
planes with 1/6
displacement vectors, were formed as a result of the coalescence of epitaxial silicide islands. Double-domain epitaxy was
found to form in RE silicides on (001)Si samples resulting from a large lattice mismatch along one direction and symmetry
conditions at the silicide/(001)Si interfaces. The orientation relationships are [0001]RESi2−x//
Si,
RESi2−x//(001)Si and [0001]RESi2−x/
Si,
RESi2−x//(001)Si. The density of staking faults in (111) samples and the domain size in (001) samples were found to decrease and
increase with annealing temperature, respectively. 相似文献
19.
Seoyong Ha Noel T. Nuhfer Gregory S. Rohrer Marc de Graef Marek Skowronski 《Journal of Electronic Materials》2000,29(7):L5-L8
Transmission electron microscopy (TEM) and KOH etching have been used to study the dislocation structure of 4H SiC wafers
grown by physical vapor transport. A new type of threading dislocation arrays was observed. Rows of etch pits corresponding
to dislocation arrays were observed in vicinity of micropipes, misoriented grains and polytypic inclusions at the periphery
of the boules and extended along the
directions. Plan view conventional and high resolution TEM showed that the arrays consisted of dislocations threading along
the c-axis with Burgers vectors having edge components of the a/3
type. The Burgers vectors were parallel to the corresponding arrays. The dislocation arrays were interpreted as slip bands
formed by dislocation glide in the prismatic slip system
of hexagonal SiC during post-growth cooling. 相似文献
20.
Tomerlin Andrew T. Edmonson William W. 《Multidimensional Systems and Signal Processing》2002,13(3):333-340
Consider the class of d-dimensional causal filters characterized by a d-variate rational function
analytic on the polydisk
. The BIBO stability of such filters has been the subject of much research over the past two decades. In this paper we analyze the BIBO stability of such functions and prove necessary and sufficient conditions for BIBO stability of a d-dimensional filter. In particular, we prove if a d-variate filter H(z) analytic on
has a Fourier expansion that converges uniformly on the closure of
, then H(z) is BIBO stable. This result proves a long standing conjecture set forth by Bose in [3]. 相似文献