Algorithmic aspects of area-efficient hardware/software partitioning

Area efficiency is one of the major considerations in constraint aware hardware/software partitioning process. This paper focuses on the algorithmic aspects for hardware/software partitioning with the objective of minimizing area utilization under the constraints of execution time and power consumption. An efficient heuristic algorithm running in O(n log n) is proposed by extending the method devised for solving the 0-1 knapsack problem. Also, an exact algorithm based on dynamic programming is proposed to produce the optimal solution for small-sized problems. Simulation results show that the proposed heuristic algorithm yields very good approximate solutions while dramatically reducing the execution time.     

Low-complex dynamic programming algorithm for hardware/software partitioning

A low-complex algorithm is proposed for the hardware/software partitioning. The proposed algorithm employs dynamic programming principles while accounting for communication delays. It is shown that the time complexity of the latest algorithm has been reduced from O(n²⋅A) to O(n⋅A), without increase in space complexity, for n code fragments and hardware area A.     

Finding optimal hardware/software partitions

Most previous approaches to hardware/software partitioning considered heuristic solutions. In contrast, this paper presents an exact algorithm for the problem based on branch-and-bound. Several techniques are investigated to speed up the algorithm, including bounds based on linear programming, a custom inference engine to make the most out of the inferred information, advanced necessary conditions for partial solutions, and different heuristics to obtain high-quality initial solutions. It is demonstrated with empirical measurements that the resulting algorithm can solve highly complex partitioning problems in reasonable time. Moreover, it is about ten times faster than a previous exact algorithm based on integer linear programming. The presented methods can also be useful in other related optimization problems.     

Exploring optimal solution to hardware/software partitioning for synchronous model

Computer aided hardware/software partitioning is one of the key challenges in hardware/software co-design. This paper describes a new approach to hardware/software partitioning for a synchronous communication model including multiple hardware devices. We transform the partitioning into a reachability problem of timed automata. By means of an optimal reachability algorithm, the optimal solution can be obtained with limited resources in hardware. To relax the initial condition of the partitioning for optimization, two algorithms are designed to explore the dependency relations among processes in the sequential specification. Moreover, we propose a scheduling algorithm to improve the synchronous communication efficiency further after partitioning stage. Some experiments are conducted with the model checker UPPAAL to show our approach is both effective and efficient. Jifeng He: On leave from East China Normal University. The work is partially supported by the 973 project 2002CB312001 of the ministry of science and technology, and the 211 project of the ministry of Education of China. Partially Supported by National Natural Science Foundation of China (No.60173003) Received November 2004 Revised July 2005 Accepted August 2005 by Eerke A. Boiten, John Derrick, Graeme Smith and Ian Hayes     

三种软硬件划分算法的比较分析

软硬件划分是嵌入式系统软硬件协同设计中的关键技术之一,如何兼顾系统的性能和成本,达到两者的最佳结合,是软硬件划分的主要问题.针对单CPU多ASICs类型的目标结构,选取了遗传算法、禁忌搜索算法和模拟退火算法等全局优化算法进行系统的软硬件划分,并对3种算法的有效性进行了比较分析.     

嵌入式系统软硬件自动划分方法研究

软硬件划分一直是嵌入式系统软硬件协同设计中的难点,如果离开具体系统,单纯的软硬件划分,其性能很难评估。本文提出基于系统体系结构,应用遗传算法来进行多目标优化的软硬件自动划分方法。在具体设计中,使用数据流图对系统建模,采用邻接表进行个体编码,定义交叉、变异操作,同时引入小生境技术,保持解的多样性。该方法为嵌入式系统软硬件自动划分提供一种新思路。     

Acceleration of software algorithms using hardware/software co-design techniques

Currently there is significant interest in the design and implementation of embedded systems where the hardware and software subsystems are developed concurrently in order to meet design constraints. We present a development environment for general-purpose systems, where the objective is to accelerate the performance of software-based applications, which are specified by C programs. Such programs may be partitioned into hardware and software subsystems — a speed-critical region of the software is implemented in an FPGA in order to provide the performance acceleration. We also discuss two versions of the underlying system hardware architecture. Practical examples are given to illustrate our approach.     

Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms

In this contribution we present a new paradigm and methodology for the Network-on-chip (NoC) based design of complex hardware/software systems. While classical industrial design platforms represent dedicated fixed architectures for specific applications, flexible NoC architectures open new degrees of system reconfigurability. After giving an overview on required demands for NoC hyper-platforms, we describe the realisation of these prerequisites within the HiNoC platform. We introduce a new dynamic hardware/software co-design methodology for pre- and post-manufacturing design. Finally we will summarize the concept combined with an outlook on further investigations.     

A hardware Memetic accelerator for VLSI circuit partitioning

During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI circuit layout. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using reconfigurable computing platforms to improve the performance of CAD optimization algorithms for the VLSI circuit partitioning problem. The proposed Genetic algorithm architecture achieves up-to 5× speedup over conventional software implementation while maintaining on average 88% solution quality. Furthermore, a reconfigurable computing based Hybrid Memetic algorithm improves upon this solution while using a fraction of the execution time required by the conventional software based approach.     

Convex regularization-based hardware/software co-design for real-time enhancement of remote sensing imagery

In this paper, we address a new approach for high-resolution reconstruction and enhancement of remote sensing (RS) imagery in near-real computational time based on the aggregated hardware/software (HW/SW) co-design paradigm. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale RS image enhancement tasks via incorporating into the fixed-point iterative reconstruction/enhancement procedures the convex convergence enforcement regularization by constructing the proper projectors onto convex sets (POCS) in the solution domain. The established POCS-regularized iterative techniques are performed separately along the range and azimuth directions over the RS scene frame making an optimal use of the sparseness properties of the employed sensor system modulation format. The hardware design is oriented on employing the Xilinx Field Programmable Gate Array XC4VSX35-10ff668 and performing the image enhancement/reconstruction tasks in a computationally efficient parallel fashion that meets the near-real time imaging system requirements. Finally, we report some simulation results and discuss the implementation performance issues related to enhancement of the real-world RS imagery indicative of the significantly increased performance efficiency gained with the developed approach.

基于自适应蚁群算法的软硬件划分

为了更好地解决软硬件双路划分问题,提出一种自适应蚁群算法．基本思想是：对状态转移概率与信息素挥发因子,采取自适应调节策略．保证了算法前期蚁群的随机性较大,可以充分全局搜索;算法后期蚁群的随机性降低,以使算法在较短的时间内收敛．对不同节点的控制数据流图进行仿真实验,表明在同等条件下,相对于改进模拟退火、改进禁忌搜索、改进蚁群算法以及ＤＣＧ３Ａ 方法,所提出算法的命中率与收敛时间结果均更优．节点规模越大,优势尤其明显．     

基于改进模拟退火算法的软硬件划分

软硬件划分是嵌入式系统协同设计中的关键问题,已经被证明是一个NP问题。模拟退火算法是解决该问题常用的启发式算法,但是其存在收敛速度过慢的问题。通过改进算法的扰动模型和退火进度,提出一种新的代价函数计算方法来提高它的收敛速度。实验结果表明,相对于基于经典的模拟退火算法和已有改进的算法,新算法运行时间大大减少,并且增大了找到近似最优解的概率。     

软硬件协同设计方法的研究

论述了嵌入式系统软硬件协同设计的一般方法,结合CORSAIR、COOL和POLIS 3种有代表性的软硬件协同设计系统,对系统描述、软硬件划分、软硬件协同综合等几个主要设计步骤进行了研究与分析,并提出了新的思路和方法。     

Efficient heuristic and tabu search for hardware/software partitioning

Hardware/software (HW/SW) partitioning is a crucial step in HW/SW codesign that determines which components of the system are implemented on hardware and which ones on software. It has been proved that the HW/SW partitioning problem is NP-hard. In this paper, we present two approaches for HW/SW partitioning that aims to minimize the hardware cost while taking into account software and communication constraints. The first is a heuristic approach that treats the HW/SW partitioning problem as an extended 0–1 knapsack problem. In the second approach, tabu search is used to further improve the solution obtained from the proposed heuristic algorithm. Experimental results show that the proposed algorithms outperform a recently reported work by up to 28 %.     

One-dimensional partitioning for heterogeneous systems: Theory and practice

We study the problem of one-dimensional partitioning of nonuniform workload arrays, with optimal load balancing for heterogeneous systems. We look at two cases: chain-on-chain partitioning, where the order of the processors is specified, and chain partitioning, where processor permutation is allowed. We present polynomial time algorithms to solve the chain-on-chain partitioning problem optimally, while we prove that the chain partitioning problem is NP-complete. Our empirical studies show that our proposed exact algorithms produce substantially better results than heuristics, while solution times remain comparable.     

NAND Flash存储控制器的软硬件划分设计

介绍了现代数码产品中NAND Flash Memory控制器的基本控制和4种软硬件划分不同的控制器设计。作者用Verilog HDL语言分别实现了这4种不同的控制器的,并进行了硬件面积、DSP占用率和接口灵活性的量化比较,指出了各种方案适用的范围。通过对一个SOC项目的需要分析,设定了基准函数,从而选出了合适的软硬件划分方案。     

粒子群优化在嵌入式软硬件划分中的应用

针对嵌入式系统设计中的软硬件划分问题,提出了一种基于粒子群优化(PSO)算法的划分策略,并将该算法与整数线性规划、遗传算法、蚁群算法等进行计算机仿真比较。结果表明,该方法获得的最优解优于遗传算法和蚁群算法两种元启发式算法,充分接近由整数线性规划得到的最优解;在算法执行时间方面,该方法也优于其它三种算法。