Grain boundary space charge region potential barrier in polycrystalline semiconductors

The grain boundary space charge region potential barrier is derived in an analytical form under equilibrium as well as non-equilibrium conditions, using various energy distributions to represent the grain boundary surface states, and the Shockley- Read-Hall theory for the carrier generation-recombination processes. The energy value of the grain boundary states is taken as a single level in the energy band gap of the semiconductor and located at the intrinsic Fermi level or displaced from it by a given amount. The restriction of the single level is later removed by permitting a certain width to the energy distribution of these states. It is shown that the results derived for non-equilibrium case reduce to the equilibrium case results derived separately, under the appropriate limit of zero excitation potential. The numerical results obtained from this formulation for the case of polycrystalline silicon are presented graphically for different values of the bulk doping concentration, grain boundary surface state density, grain boundary state energy distributions and the excitation potential, under equilibrium and non-equilibrium conditions. It is found that the grain boundary energy states located higher than the intrinsic Fermi level give greater values of grain boundary potential barrier height for a p-type semiconductor and the reverse applies to an n-type semiconductor. Further a wider energy distribution of these states gives rise to a towering of the potential barrier height at the grain boundary. Under non-equilibrium conditions, it is seen that the grain boundary barrier height remains unaltered for values of the excitation potential below a certain threshold which in turn depends upon the bulk dopant concentration in the semiconductor and the grain boundary surface state density and its energy distribution. Above this threshold value the barrier height reduces nearly linearly with the increase of the excitation potential with a slope lying-between ?0.5 and ? 1.0. For comparison with the available experimental results of Seager and Castner for n-type polycrystalline silicon we have obtained the grain boundary surface density and energy distribution parameters that provide excellent matching with the experimentally determined variation of the grain boundary potential barrier height with the dopant concentration in the range of 10¹³ to 10¹⁷/cm³, and based upon these parameters we have calculated the non-equilibrium barrier heights at different excitation potentials for this experimental case. A comparison is also made with Seager's experimental observations of non-equilibrium grain boundary barrier height for n-type silicon bicrystals in the illumination range of 3 × 10^?6 to 3 × 10^?2 SUN. For particular values of the density of grain boundary surface states and their energy distribution parameters, we could match our theoretical results with his experimental observations of barrier height.     

Thermoelectric Properties of Polycrystalline Thin Films Under an External Magnetic Field

A theoretical model is proposed to predict the Seebeck coefficient and the electrical conductivity for a polycrystalline thermoelectric (TE) thin film under an external magnetic field. The model considers the distribution of electrons in the microstructure of TE thin-film materials, taking the scattering effect of electrons at the grain boundary as the boundary condition for electron transport in the grain. The transmission coefficient is introduced to describe the probability of electrons passing through the grain boundary potential barrier, while the relationships between the Seebeck coefficient, the electrical conductivity, and the transmission coefficient are studied. Furthermore, the results from the calculations of the Seebeck coefficient, the electric conductivity, and the power factor of TE materials under various applied magnetic fields, transmission coefficients, and grain sizes indicate that the applied external magnetic field has a very significant influence on the TE properties of polycrystalline thin films.     

Modeling the gate bias dependence of contact resistance in staggered polycrystalline organic thin film transistors

We have modeled the dependence on the gate voltage of the bulk contact resistance and interface contact resistance in staggered polycrystalline organic thin film transistors. In the specific, we have investigated how traps, at the grain boundaries of an organic semiconductor thin film layer placed between the metal electrode and the active layer, can contribute to the bulk contact resistance. In order to the take into account this contribution, within the frame of the grain boundary trapping model (GBTM), a model of the energy barrier E_B, which emerges between the accumulation layer at the organic semiconductor/insulator interface and injecting contact, has been proposed. Moreover, the lowering of the energy barrier at the contacts interface region has been included by considering the influence of the electric field generated by the accumulation layer on the injection of carriers at the source and on the collection of charges from the accumulation layer to the drain contact. This work outlines both a Schottky barrier lowering, determined by the accumulation layer opposite the source electrode, as well as a Poole-Frenkel mechanism determined by the electric field of the accumulation layer active at the drain contact region. Finally it is provided and tested an analytical equation of our model for the contact resistance, summarizing the Poole-Frenkel and Schottky barrier lowering contribution with the grain boundary trapping model.     

集成电路中金属连线下多晶硅电阻的不稳定性分析及抑制方法

作为集成电路的电阻单元,掺硼的多晶硅电阻在千欧级的范围内存在阻值不稳定性,尤其在金属连线下更为严重．分析了不同工艺条件下制作的多晶硅电阻电特性和晶格特性．结果表明,阻值的不稳定性主要由载流子迁移率改变引起．通过测试和运用Seto’s模型计算进一步发现,在铝连线底下势垒高度和俘获的电荷密度均有降低．电荷的俘获／反俘获在多晶硅晶粒边界发生引起势垒高度的变化,从而导致阻值不稳定．然后,借助于补偿的离子注入制作了高稳定的、阻值在千欧级的多晶硅电阻．该方法使得多晶硅晶粒边界电荷的俘获／反俘获对氢退火不敏感．     

钛酸钡基热敏电阻器低温调阻法

通过陶瓷与酸的相互作用，使钛酸钡基ＰＴＣＲ陶瓷材料烧成样品的阻值上升。酸处理工艺条件对阻值上升幅度有一定影响。酸处理后的样品的综合电性能的变化，确定了用酸处理升高阻值的可行性。运用复阻抗分析法对样品阻值上升前后晶粒、晶界电阻的变化进行了研究。分析了酸处理过程中阻值变化的规律。运用叠加势垒模型分析了酸处理使阻值升高的机理。     

一维无公度系统的迁移率边

应用增长因子判据,研究了一维无公度系统Soukoulis-Economou模型电子态的局域性质,得到了该模型的局部迁移率边,进一步证实了应用Landauer公式计算电阻得出的迁移率边结构.     

Model of low frequency noise in polycrystalline silicon thin-filmtransistors

A model for the low frequency noise of polycrystalline silicon thin film transistors (polysilicon TFTs) is proposed. The model takes into account fluctuations of the grain boundary potential barrier induced by those of the grain boundary interface charge and fluctuations of carriers due to trapping in oxide traps located close to the interface. Using the proposed model, it is demonstrated that both grain boundary and oxide traps can be determined in polysilicon TFTs from noise measurements     

Enhanced channel mobility in polysilicon thin film transistors

Due to scattering by charged grain boundaries, carrier mobility μ in the channel of polysilicon thin film transistors (TFT) is usually much lower than the bulk silicon value. We have studied a series of _p-channel TFT devices with varying gate oxide thicknesses d_ox and found that CL shows a strong increase when d_ox is reduced below 150 Å. We attribute this effect to the screening of the charged grain boundary by the gate conductor. The screening becomes effective when the characteristic length associated with the potential barrier at charged grain boundaries becomes comparable to the optical distance between the grain boundary charge and its mirror image in the gate electrode. From the known structure parameters the onset of the strong screening is estimated to occur at oxide thicknesses of about 100 Å     

Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel

A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel.     

氧化物掺杂ZnO-BST复合陶瓷的复阻抗分析

采用复阻抗分析方法研究了Sb2O3、MnO及Cr2O3掺杂对复合陶瓷ZnO-0.17Ba0.8Sr0.2TiO3(ZnO-0.17BST)晶粒相、晶界相电阻的影响,采用XRD、SEM测量了试样的晶相、微观形貌。结果表明:掺杂并没有改变复合陶瓷的相组成,Sb2O3掺杂,Sb2O3-MnO共掺杂和Sb2O3-MnO-Cr2O3共掺杂的三组试样,其晶粒相电阻随掺杂试剂种类的增多依次减小,晶界相电阻先减小后增加。掺杂氧化物不同,其晶粒、晶界相电阻对复合体系电阻的贡献不同。考虑到晶界相的含量,在掺杂ZnO-0.17BST复合陶瓷电导中,晶粒相起主导作用。     

无飘移电迁移理论(扩散产生复合俘获理论)

电迁移是在高电流密度下金属导体中原子输运,它在导体中产生空位,增加导体的电阻.Huntington于1961年描述电迁移;Black于1969年推导经验电阻公式用以模拟电迁移,给出电阻和失效实验数据对电流密度和温度的依赖关系.Tan于2007年总结Black经验公式在连接晶体管和其他硅集成电路器件的导线方面四十年运用情况.自1957年第一个Landauer理论以来,理论工作者用50年试图论证飘移力,即Black假设的电子动量转移,又称电子风力,作用到金属原子和离子上,可使它们移动.Landauer于1989年断定,即使运用最基本和完备的多体量子输运理论,电子风力也站不住脚.本文回顾用于金属导线的无飘移或无电子风力原子空位模型.萨在八十年中提出这模型,在1996年以课外作业题解的形式描述这模型.该模型解释了用Black经验公式拟合的电阻实验数据的电流和温度依赖关系.得到精确解析方程,描述两种极限情形下金属导线电阻或电流,R(t)/R(0)=J(t)/J(0)=[1-2(t/τα)1/α]-1/2:从低到高电流密度,价键断裂情形α=1～2和原子扩散情形α=2～4.其中τα是电迁移机理的时间特征常数,含有价键断裂率,原子扩散系数和激发能.     

Bi2O3对TiO2系压敏陶瓷性能的影响

采用传统电子陶瓷工艺制作了TiO2系压敏陶瓷。通过测试其I-V特性、复阻抗特性、晶界电阻、晶粒电阻及势垒高度,研究了Bi2O3对TiO2-Bi2O3-Nb2O5-SrO系压敏陶瓷微结构及电性能的影响。结果表明,Bi2O3的适当掺杂范围在0.3%~0.5%(摩尔分数)。其掺杂量的变化,可显著改变TiO2-Bi2O3-Nb2O5-SrO系压敏陶瓷的晶界电阻及势垒高度,进而对压敏陶瓷的电学非线性特性产生影响。当x(Bi2O3)为0.4%时,压敏陶瓷的V1mA与α分别为40V/mm与6.2。     

四价添加剂掺杂ZnO压敏电阻器的性能

基于理论研究的结果,用固相法研究了四价添加剂对ZnO压敏电阻器性能的影响和作用机理.结果表明,优选的四价添加剂掺杂能有效降低ZnO晶粒的电阻率和残压比;通过提高晶界氧的电离度,可使晶界势垒高度上升,提高了ZnO的压敏电压梯度.     

Impedance Analysis of Grain Barrier Potential in SnO2 Gas Sensors^①②

The potential barrier(or“grain boundaries”)of SnO2 gas sensor is the dominant factor of conductivity.A new simple method is applied to study the grain boundary using impedance analyzer under different DC bias.A model is presented to explain the experiment results.The model predicts height of the grain boundary under different humidity conditions,as well as grain size.The role of water is discussed.This model can be applied with ease to study the role of other reducing gasses.     

Current transport across a grain boundary in polycrystalline semiconductors

A unified approach to current transport across a grain boundary in polycrystalline semiconductors is developed. The resulting expressions for potential barrier and J-V characteristics are of general validity, in contrast to the many derivations of previous models, each with its own conditions of validity. The study concentrates on the carrier-trapping effect, and the trapping-state density can be monoenergetic, continuous, gaussian, or any reasonable distribution. By solving Possion's equation under suitable boundary conditions without the depletion approximation, a single formulation is obtained for potential barriers in two adjacent grains with different sizes and doping levels. The grain-boundary scattering effect is approximated as a rectangular potential barrier. The voltage division of an applied bias across the junction is determined under the current-continuity conditions. A single expression with suitable computational simplicity is then presented for the J-V characteristics across the many-valley semiconductor/grain-boundary/semiconductor junction. It uses the generalized WKB approximation and Fermi-Dirac statistics, and also considers the ellipsoidal energy surfaces of different valleys. All the thermionic, thermionic-field, and field emissions are included. As a result, the approach is valid for many-balley semiconductor materials over a wide range of temperatures, trapping-state density distributions, doping concentrations, grain sizes, and crystalline orientations.     

Control of the performance of polysilicon thin-film transistor byhigh-gate-voltage stress

The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFTs) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases after negative high gate voltage stress. The experimental results indicate that Ca and Al ions or hydrogen atoms existing in the gate oxide may be able to passivate grain boundaries at the polysilicon-SiO₂ interface     

低压ZnO压敏陶瓷晶界特性的研究

借助 HP4192 A低频阻抗分析仪 ,分析了低压 Zn O压敏陶瓷的 C- V特性及介电和损耗特性、添加物对Zn O压敏瓷晶界电学特性的影响。探讨了热处理气氛对 Zn O晶粒边界电性能的作用机理。实验结果表明 :Na+ 掺杂量增加时 ,施主浓度基本保持不变 ,而势垒高度、界面态密度和耗尽层宽度增加 ;在空气中退火 ,样品的施主浓度减少 ,势垒高度降低 ;在 Ar气中退火样品的施主浓度基本保持不变 ,而势垒高度下降较大 ;在音频范围内 ,Zn O压敏瓷具有很高的介电常数 (εr约 130 0 ) ;在 10 5～ 10 6 Hz范围内 ,εr下降较明显 ,与此对应 ,介质损耗角正切 tgδ在 10 5～ 10 6 Hz范围内出现一个峰值 ,该峰具有扩展的德拜驰豫峰特征     

Effect of alkali metals on the electronic properties of grain boundaries on a polycrystalline silicon surface

The effect of alkali metals on carrier drift from grain boundaries to a polycrystalline silicon surface is experimentally studied. The results obtained show that an increase in the dopant concentration during the diffusion, desorption, and adsorption of alkali metals along grain boundaries leads to an increase in the potential barrier.     

ZnO薄膜紫外光敏特性及晶界势垒的研究

以二水合醋酸锌为原料,采用sol-gel法在石英衬底上制备了ZnO薄膜。用AFM观察表面形貌,通过测量真空条件下不同温度热处理后薄膜的I-V特性,拟合计算晶界势垒高度。研究了热处理温度对ZnO薄膜性能的影响。结果表明:经650℃热处理制备的ZnO薄膜样品具有较佳性能,结构均匀致密,粒径分布为20～32nm。在10V偏压和1.24×10–3W/cm2光强下,紫外光灵敏度为43.95;无光照条件下晶界势垒高度为0.079eV。紫外光照使晶界势垒高度下降为0.011eV,薄膜的紫外光灵敏度与势垒高度的相对变化密切相关。     

On the barrier height of a metal-semiconductor contact with a thin interfacial layer

The free surface potential of a semiconductor has been studied by using a generalised definition of “neutral level.” Following this definition, an expression for the barrier height of an MIS structure has been derived, from which the expression for barrier height as derived by Cowley and Sze follows as a special case. Lastly, the formula used by previous workers for the determination of neutral level, has been modified for a more accurate calculation of the said parameter.