Plasma-Induced Defect-Site Generation in Si Substrate and Its Impact on Performance Degradation in Scaled MOSFETs

Plasma-induced ion-bombardment damage was studied in terms of defect sites created underneath the exposed Si surface. From the shift of capacitance–voltage ($C$– $V$) curves, the defect sites were found to capture carriers (being negatively charged in the case of an Ar plasma exposure). This results in a change of the effective impurity-doping density and the profile. We also report that the defect density depends on the energy of ions from plasma. A simplified and quantitative model is proposed for the drain–current degradation induced by the series-resistance increase by the damage. The relationship derived between the defect density and the drain–current degradation is verified by device simulations. The proposed model is useful to predict the device performance change from plasma process parameters.      

基于AlGaN/GaN HEMT的源漏整体刻蚀欧姆接触结构

研究了源漏整体刻蚀欧姆接触结构对AlGaN/GaN高电子迁移率晶体管(HEMT)的欧姆接触电阻和金属电极表面形貌的影响.利用传输线模型(TLM)对样品的电学性能进行测试,使用原子力显微镜(AFM)对样品的表面形貌进行表征,通过透射电子显微镜(TEM)和X射线能谱仪(EDS)对样品的剖面微结构和界面反应进行表征与分析.实验结果显示,采用Ti/Al/Ni/Au(20 nm/120 nm/45 nm/55 nm)金属和源漏整体刻蚀欧姆接触结构,在合金温度870 c℃,升温20 s,退火50 s条件下,欧姆接触电阻最低为0.13 Ω·mm,方块电阻为363.14 Ω/□,比接触电阻率为4.54×10-7Ω·cm2,形成了良好的欧姆接触,降低了器件的导通电阻.     

A normally off GaN n-MOSFET with Schottky-barrier source and drain on a Si-auto-doped p-GaN/Si

We have fabricated an enhancement-mode n-channel Schottky-barrier-MOSFET (SB-MOSFET) for the first time on a high mobility p-type GaN film grown on silicon substrate. The metal contacts were formed by depositing Al for source/drain contact and Au for gate contact, respectively. Fabricated SB-MOSFET exhibited a threshold voltage of 1.65 V, and a maximum transconductance(g/sub m/) of 1.6 mS/mm at V/sub DS/=5V, which belongs to one of the highest value in GaN MOSFET. The maximum drain current was higher than 3 mA/mm and the off-state drain current was as low as 3 nA/mm.     

栅槽刻蚀工艺对增强型GaN HEMT器件性能的影响

基于凹槽栅增强型氮化镓高电子迁移率晶体管(GaN HEMT)研究了不同的栅槽刻蚀工艺对GaN器件性能的影响。在栅槽刻蚀方面,采用了一种感应耦合等离子体(ICP)干法刻蚀技术与高温热氧化湿法刻蚀技术相结合的两步法刻蚀技术,将AlGaN势垒层全部刻蚀掉,制备出了阈值电压超过3 V的增强型Al_2O_3/AlGaN/GaN MIS-HEMT器件。相比于传统的ICP干法刻蚀技术,两步法是一种低损伤的自停止刻蚀技术,易于控制且具有高度可重复性,能够获得更高质量的刻蚀界面,所制备的器件增强型GaN MIS-HEMT器件具有阈值电压回滞小、电流开关比(I_ON/I_OFF)高、栅极泄漏电流小、击穿电压高等特性。     

Effects of Self-Heating on Performance Degradation in AlGaN/GaN-Based Devices

A self-consistent electrothermal transport model that couples electrical and thermal transport equations is established and applied to AlGaN/GaN device structures grown on the following three different substrate materials: 1) SiC; 2) Si; and 3) sapphire. Both the resultant I-V characteristics and surface temperatures are compared to experimental I -V measurements and Raman spectroscopy temperature measurements. The very consistent agreement between measurements and simulations confirms the validity of the model and its numerical rendition. The results explain why the current saturation in measured I-V characteristics occurs at a much lower electric field than that for the saturation of electron drift velocity. The marked difference in saturated current levels for AlGaN/GaN structures on SiC, Si, and sapphire substrates is directly related to the different self-heating levels that resulted from the different biasing conditions and the distinctive substrate materials.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

凹槽场效应晶体管栅源电阻的计算

本文借助保角变换导出了计算凹槽场效应晶体管栅源电阻的近似公式.考虑了一系列的凹槽几何结构,平沟道作为其中的一个特例.分析表明,器件的几何参数(包括沟道厚度、挖槽比,以及栅源间距)对于所讨论的电阻及其公式的适用性是至关重要的.文章指出,特别是在短栅源间距的情况下,深槽将导致较大的沟道串联电阻,因此在满足接触电阻符合要求的条件下,应采用较浅的挖槽结构为宜.     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

高性能硅双极器件的发展

以ECL电路为主,讨论了硅双极器件近期的发展。简述了VLSI中ECL电路结构和性能之后,着重讨论双极器件的按比例缩小、结构的改进以及相关的工艺技术的发展,最后分析了双极器件的低温工作性能。     

Effect of Al Composition and Gate Recess on Power Performance of AlGaN/GaN High-Electron Mobility Transistors

AlGaN/GaN high-electron mobility transistors with different Al compositions and barrier thicknesses were compared. The samples with higher Al composition and similar 2D electron gas density showed higher gate leakage, utilizing a slant field plate gate process. By applying a gate recess etch and a slant field plate gate process, gate leakage was improved to a similar level for all the devices, and the power density and PAE were much improved.     

Si含量对激光合金化TiC/CrxCy陶瓷涂层组织性能影响的研究

实验涂层材料以亚微米级TiC和CrxCy为强化硬质相,Fe-Cr合金为其基础粘结相,并加入特定含量的Si元素,运用激光合金化技术,在球墨铸铁表面制备出高硬度的合金化层.利用XRD、SEM、EDS等分析不同Si含量激光合金化层的相组成及显微组织,并测试其维氏硬度.结果表明:激光合金化层表面平整,并与基体实现了良好的冶金结合,形成以莱氏体与马氏体为主的显微组织;随着硅含量的提高,相和组织发生了一定变化,合金化层硬度也随之提高.     

MEMS开关封装结构热形变对芯片性能的影响

模拟了处在一定功率密度或不同温度下封装结构贴片的形变引起的X波段MEMS开关芯片的形变,从而导致的开关芯片性能的变化。用Coventor软件模拟出在开关衬底为200μm,贴片处功率密度为300pW/μm2时,开关芯片的形变量为0.142μm;开关衬底为300μm,温度为373K时,开关芯片的形变量为0.791μm。进一步用HFSS模拟出开关的插入损耗在中心频率10GHz处由封装前的0.042dB和0.022dB变化为封装后的0.078dB和0.024dB。     

Si1-xGex/Si多层异质外延结构的研究

对制作的Ｓｉ１－ｘＧｅｘ／Ｓｉ多层异质外延结构进行了研究。并对其做了反射高能电子衍射（ＲＨＥＥＤ）、Ｘ射线衍射（ＸＲＤ）和扩展电阻（ＳＲ）等测量,给出了利用这种结构研制出的异质结双极晶体管（ＨＢＴ）的输出特性曲线。     

硼硅对BST薄膜结构和性能的影响

用sol-gel法制备0.5mol/L钛酸锶钡(Ba0.7Sr0.3TiO3)前驱溶液,并在其中加入硼、硅成功地制备了室温下具有优良铁电性质的BSTS薄膜。XRD及DSC分析显示,BSTS薄膜呈现钙钛矿结构。测试结果表明,随着硼、硅的加入量增加,其εr和tgδ明显降低。当硼、硅的加入量小于10mol/L时,薄膜的漏电流比没有加入硼、硅的BST薄膜的低,当硼、硅的加入量大于15mol/L时,薄膜的漏电流比没有加入硼、硅的BST薄膜的高。     

煅烧温度和恒温时间对ZnO/AAO/Si组装体系的影响

以AAO/Si为模板,采用化学气相沉积(CVD)的方法在不同温度下,通过煅烧Zn粉和C粉的混合物制备ZnO/AAO/Si组装体系,并对其结构和性质进行了研究。扫描电镜(SEM)结果表明:随着煅烧温度的升高,AAO表面的孔洞逐渐被封堵,当温度达到900℃时,在AAO的表面出现了一层ZnO薄膜。X射线衍射(XRD)结果显示,700℃时在XRD图谱上观看到六角纤锌矿的ZnO的衍射峰,并且随着温度的升高,ZnO的衍射峰逐渐增强,当温度升至800和900℃时出现了ZnAl2O4的衍射峰。因此,化学气相沉积制备组装体系时的最适温为700℃。在700℃时煅烧不同恒温时间制备的ZnO/AAO/Si组装体系SEM图显示,随着恒温时间的延长,孔的封闭效应逐渐明显。     

基于Bayes性能退化模型的可靠性评定

结合航空航天推进系统可靠性试验小于样的特点,在小子样条件下,首先对基于Bayes方法性能退化轨道参数的计算模型进行研究．然后结合随机变量菌数的分布的计算,推导出系统可靠性后验估计和置信下限估计的计算公式。在理论推导的基础上,结合工程实饼说明该方法的有效性。     

基于加速性能退化试验的板级可靠性评估

传统的可靠性评估方法一般基于失效寿命数据,而目前对于高可靠长寿命的电子产品,很难通过加速试验获得其失效寿命时间。为解决这一矛盾,将性能退化理论引入到传统可靠性评估中,提出了基于失效数据及加速性能退化的可靠性评估的新方法。应用某型雷达24V/2A稳压电源板加速性能退化试验进行验证,结果表明该方法用于高可靠长寿命电子装备的可靠性评估是正确有效的。     

基于加速性能退化的元器件贮存寿命预测

提出了基于加速性能退化的元器件贮存寿命预测流程,重点对元器件退化轨迹模型的建立和加速退化试验数据处理方法进行了研究。应用非线性的曲线拟合法来建立退化轨迹模型,并评价其拟合优度。加速退化试验数据的处理主要应用伪寿命分布与加速退化模型拟合的方法。从而外推正常应力水平下元器件的贮存寿命。最后,应用所提出的贮存寿命预测方法对某型钽电容的贮存寿命进行了预测。并验证了该方法具有一定的效用性。     

低阻硅基厚膜聚酰亚胺上共面波导的损耗特性

制备了一种低阻硅基厚膜聚酰亚胺上的高性能共面波导传输线 ,并从理论上分析了传输线损耗的成因及其计算方法。聚酰亚胺膜厚 1 1 .5 μm的低阻硅 (0 .5 Ω·cm)上的共面波导传输线在 1 0 GHz下插入损耗为3 .5 d B/cm。然而 ,相同衬底上 ,无聚酰亚胺膜的共面波导传输线在 1 0 GHz下插入损耗为 5 0 d B/cm,损耗特性明显比前者差。测试结果表明聚酰亚胺层的介入能有效地改善传输线的损耗特性 ,且损耗随着聚酰亚胺膜厚的增加而降低。     

硅基LiNbO3薄膜的工艺研究及其性能分析

利用射频磁控溅射法在硅衬底上生长c轴取向LiNbO3薄膜.研究了生成高质量薄膜的实验条件和快速退火处理对薄膜结晶质量的影响.发现以600℃衬底温度制备薄膜并以650℃进行快速退火时获得了具有优异结晶质量的LiNbO3薄膜.采用扫描电镜分别对薄膜的表面、截面进行了分析.结果表明,薄膜表面光滑,晶粒均匀致密.