一个1GHz两倍泵的多端口寄存器堆的设计

对于流水线型的超大规模微处理器,通常采用多端口的寄存器堆暂存中间数据,这些读写操作势必增加寄存器堆的芯片面积和功耗。因此提出一种基于double-pumped的采样时钟,在一个系统时钟周期内用一根复用地址线顺序完成读写操作,从而大大减少芯片面积,并降低系统功耗。采用1.2V,0.13!m的CMOS工艺进行仿真,结果显示该2读1写寄存器堆在1GHz工作频率下,其数据读取时间仅为546ps。     

高速低功耗6端口分块式寄存器堆的设计

在SMIC的0.18μm CMOS工艺下,设计了一款3读3写32×16bit高速低功耗寄存器堆.该寄存器堆采用分块结构和改进的存储单元,有效地降低了寄存器堆的功耗.电路仿真表明,在室温条件下,工作电压为1.8V,最大读写延时为0.9ns,当寄存器堆工作在1GHz时,功耗为23.70mW.     

65nm下低功耗稳定性高的寄存器堆的设计

本文详细分析了低功耗稳定性高的32x32, 4读2写的寄存器堆,提出了采用MUX和锁存器的输出结构。该输出结构没有任何动态或模拟电路,提高了鲁棒性的同时降低了功耗。简化的时序不仅降低了功耗,而且增强了鲁棒性。连续读“0”或“1”的时候,这种结构能够消耗更小的功耗。该寄存器堆已在65nm下流片,芯片测试结果显示,它1.2V电源电压下,工作频率为0.8GHZ,消耗功耗7.2mW。     

6端口CMOS寄存器堆设计

高性能超标量处理器完成多条指令并行,需要寄存器堆提供多端口、高速访问.本文介绍一个0.18μmCMOS工艺下的四读二写6端口寄存器堆的全定制设计,它采用改进的多端口存储器单元结构和基于NAND结构的低功耗译码器,并且设计了内部时钟生成部件来提高工作频率.寄存器堆通过功能验证和性能测试,可以工作在450MHz频率上,功耗为36mW,面积0.06mm2,参考综合结果具有高速、低功耗和面积小的特点.     

多端口寄存器堆的低功耗设计方法

随着半导体工艺的飞速发展和芯片工作频率的提高,芯片的功耗迅速增加,导致芯片发热量的增大和可靠性的下降。因此,功耗成为集成电路设计中的一个重要考虑因素。寄存器堆作为微处理器的关键部件,为了满足其运算速度和指令级并行的流水线结构,高速和多端口读写成为发展的必然趋势,其低功耗设计对降低整个处理器的功耗具有重要的意义。读写位线、负载电容、灵敏放大器、时钟翻转等是影响寄存器堆总功耗的重要因素。针对各因素进行低功耗设计成为寄存器堆设计的关键。     

减小SoC系统测试功耗的方法

系统功耗主要取决于系统电源电压、负载电容及节点电平的翻转概率。前两种方法对减少SoC测试功耗的作用非常有限,而通过改变扫描寄存器的结构．即采用扫描阵列结构可以极大的降低SoC测试功耗。     

基于低功耗的BIST测试生成结构优化设计

针对内建自测试(Built-In Self-Test,BIST)技术的伪随机测试生成具有测试时间过长,测试功耗过高的缺点,严重影响测试效率等问题,提出一种低功耗测试生成方案,该方案是基于线性反馈移位寄存器(LFSR)设计的一种低功耗测试序列生成结构--LP-TPG(Low Power Test Pattern Generator),由于CMOS电路的测试功耗主要由电路节点的翻转引起,所以对LFSR结构进行改进,在相邻向量间插入向量,这样在保证原序列随机特性的情况下,减少被测电路输入端的跳变,以ISCAS'8585基准电路作为验证对象,组合电路并发故障仿真工具fsim,可得到平均功耗和峰值功耗的降低,从而达到降低功耗的效果.验证结果表明,该设计在保证故障覆盖率的同时,有效地降低了测试功耗,缩短了测试序列的长度,具有一定的实用性.     

可写穿的16端口存储单元定制设计

为使高性能超标量处理器能够完成多条指令并行，寄存器堆需要提供多端口的高速访问。文章介绍了一种可写穿的16端口寄存器堆存储单元设计，在1.8V0．18μm CMOS工艺下，该存储单元的10个读口和6个写口均可以独立访问。存储单元设计中考虑了紧凑性、可靠性和功耗问题，并且制定了长线规划来减少版图设计中串扰噪声对功能的影响。仿真结果表明，该存储单元可以作为一种更优的实现方法。工作在500MHz主频下的寄存器堆内。     

带复位的高性能译码器设计

译码器是寄存器文件中的关键部件.为了实现高性能的寄存器文件,结合寄存器文件的设计,实现了一款带复位的高性能译码器,并分析了这款译码器的性能和功能.设计中,使用了偏斜逻辑的设计方法,有效地提高了译码器的速度.同时,采用特殊的复位电路,可以精确地控制字线维持时间,降低功耗.在0.13μm工艺下对译码器进行模拟分析并与传统的译码器进行比较,结果表明,相对于传统静态译码器,该译码器的速度增加了43.24%,延时为210ps,相对于传统动态译码器,平均功耗降低了37.56%.     

基于脉冲寄存器的高性能低功耗电路设计实现

提出了一种高速低功耗脉冲寄存器的设计方法,并将其应用在高速DSP地址生成单元的设计中.仿真结果表明,文中提出的脉冲寄存器结构较传统的寄存器在速度、面积、功耗等指标上均有显著的提高.     

一种新型低功耗准动态移位寄存器的模拟

提出一种低功耗准动态移位寄存器电路 ,这种电路静态功耗几乎为 0 ,仅仅存在动态功耗 ;是一种无比电路 ,所有的开关和反相器晶体管按最小尺寸进行设计 ,电路简单 ,面积小 ;该种电路不存在电荷的再分配 ,漏电流损失的电荷可从电源补充。采用 1 .2μm的 CMOS工艺 ,用 PSPICE8.0对该电路进行仿真验证。这种低功耗准动态移位寄存器电路已成功用作 CMOS图像传感器的读出扫描电路。     

Adopting the Banked Register File Scheme for Better Performance and Less Leakage

Excessively high temperature deteriorates the reliability and increases the leakage power consumption of microprocessors. The register file, known as one of the hottest functional units in microprocessors, incurs frequent dynamic thermal management operations for thermal control. In this letter, we adopt the banked register file scheme, which was originally proposed to reduce dynamic power consumption. By simply modifying the register file structure, the temperature in the register file was reduced dramatically, resulting in 13.37% performance improvement and 10.49% total processor leakage reduction.     

一种基于电阻型数模转换器每级输出3位的6-bit 410-MS/s单通道异步逐次逼近模数转换器

该设计采用SMIC 65-nm CMOS工艺,实现了一款可应用于超宽带通信领域的单通道低功耗6位410-MS/s异步逐次逼近模数转换器(SAR ADC)。通过采用电阻型数模转换器、每级输出3位数字码字结构,以及改进的异步控制逻辑,该ADC在370-MS/s采样率时,无杂散动态范围(SFDR)达到41.95-dB,信号噪声失真比(SNDR)达到28.52-dB。在采样率为410MS/s时,该设计仍能达到40.71-dB的SFDR和30.02-dB的SNDR。通过动态比较器的使用,实现了低功耗设计。测试结果表明,在410-MS/s采样率下,电路总功耗为2.03mW,对应的品质因子(FOM)为189.17fJ/step。     

基于互补谓词的编译优化

许多通用和嵌入式高性能处理器都支持谓词执行,利用谓词执行可以简化程序的控制结构,而且指令调度、寄存器分配也可以利用谓词提高效率.基于二进制决策图(BDD)的谓词分析系统,提出了一种利用互补谓词机制对控制结构进行优化的方法;对传统着色图寄存器分配算法进行改进,给出了一种利用互补谓词机制建立统一简化干涉图的新算法,减少了代码溢出;利用互补谓词的特性指导指令调度,使之更加有效利用资源,并对目标体系结构进行了改进以支持指令调度.最后在YHFT-DSP/700芯片的编译器上对所提优化方法的有效性进行了验证.     

Cluster-based adaptive power control protocol using Hidden Markov Model for Wireless Sensor Networks

This paper presents strategies for an efficient and dynamic transmission power control technique, in order to reduce packet drop and hence energy consumption of power-hungry sensor nodes operated in highly non-linear channel conditions of Wireless Sensor Networks. Besides, we also focus to prolong network lifetime and scalability by designing cluster-based network structure. Specifically we consider weight-based clustering approach wherein, minimum significant node is chosen as Cluster Head (CH) which is computed stemmed from the factors distance, remaining residual battery power and received signal strength (RSS). Further, transmission power control schemes to fit into dynamic channel conditions are meticulously implemented using Hidden Markov Model (HMM) where probability transition matrix is formulated based on the observed RSS measurements. Typically, CH estimates initial transmission power of its cluster members (CMs) from RSS using HMM and broadcast this value to its CMs for initialising their power value. Further, if CH finds that there are variations in link quality and RSS of the CMs, it again re-computes and optimises the transmission power level of the nodes using HMM to avoid packet loss due noise interference. We have demonstrated our simulation results to prove that our technique efficiently controls the power levels of sensing nodes to save significant quantity of energy for different sized network.     

Distributed sleep transistor network for power reduction

Sleep transistors are effective to reduce leakage power during standby modes. The cluster-based design was proposed to save sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and inserting a sleep transistor per cluster. In this paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the cluster-based design in terms of the sleep transistor area and circuit performance. We reveal properties of optimal DSTN designs, and then develop an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs. Furthermore, we present custom layout designs to verify the area reduction by DSTN.     

标识信息处理技术在税控收款机产品可追溯管理中的研究与应用

针对税控收款机产品可追溯性的要求，制定出了“税控收款机生产企业资质认定”后续监督管理体系具体的标识方案，并在此基础上制定了标识信息处理的信息系统。     

Energy and Trust Management Framework for MANET using Clustering Algorithm

In General, Mobile Ad-Hoc Network (MANET) has limited energy resources, and it cannot recharge itself. This research goal focuses on building a power management scheme that saves energy in the MANET. Due to power instability, there is a chance that cluster heads fail and function incorrectly in cluster-based routing. As a result, instability occurs with the cluster heads while collecting data and communicating with others effectively. This work focuses on detecting the unstable cluster heads, which are replaced by other nodes implementing the envisaged self-configurable cluster mechanism. A self-configurable cluster mechanism with a k-means protocol approach is proposed to designate cluster heads effectively. The proposed k-means procedure is based on periodic irregular cluster head rotations or altering the number of clusters. We also propose a trust management mechanism in this research to detect and avoid MANET vulnerabilities. Because of the continuously changing topology and limited resources (power, bandwidth, computing), the trust management algorithm should only use local data. Consequently, compared to traditional protocols, the proposed approach with the k-means procedure and its experimental results show lower power usage and provide an optimal system for trust management.

     

基于低摆幅策略的低功耗多端口寄存器文件设计

本文通过使用低摆幅策略和修改的与非型地址译码器设计了一种低功耗的寄存器文件。该低摆幅策略基于反馈机制并利用动态逻辑减少主动反馈引入的功耗。低摆幅策略分为读写两部分。在低摆幅写策略中,设计了一种存储单元用来支持低摆幅写入。修改后的NAND解码器,不仅功耗更低,同时面积也大幅减少。对比传统单端位线的寄存器文件,低摆幅技术在读和写部分能分别降低51.15%和34.5%的功耗。后仿结果表明在十二个端口同时工作时,低摆幅策略能够降低39.4%的功耗。     

税控系统数据稳健性的方案设计

税控收款机涉及到大量的安全性问题,数据的安全性、稳健性是其中很重要的一方面。首先介绍了税控收款机中数据的安全存储机制,分析了YAFFS文件系统的特性。为了提高数据存储的安全性并能够兼顾成本因素,在YAFFS文件系统基础上,提出了一种利用NandFlash存储器能够一次擦除多次写入的特殊性质,不使用储能元件的掉电保护设计方案。