High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

Performance and reliability of low-temperature polysilicon TFT with a novel stack gate dielectric and stack optimization using PECVD nitrous oxide plasma

This paper proposes a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si thin-film transistors, composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O plasma. The novel stack gate dielectric exhibits a very high electrical breakdown field of 8.5 MV/cm, which is approximately 3 MV/cm higher than traditional PECVD TEOS oxide. The novel stack oxide also has better interface quality, lower bulk-trap density, and higher long-term reliability than PECVD TEOS dielectrics. These improvements are attributed to the formation of strong Si/spl equiv/N bonds of high quality ultra-thin oxynitride grown by PECVD N/sub 2/O plasma, and the reduction in the trap density at the oxynitride/poly-Si interface.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.     

A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.     

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.     

Ultrathin aluminum oxide gate dielectric on N-type 4H-SiC prepared by low thermal budget nitric acid oxidation

MOS capacitors with an ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric were fabricated on n-type 4H-SiC. Al/sub 2/O/sub 3/ was prepared by room-temperature nitric acid (HNO/sub 3/) oxidation of ultrathin Al film followed by furnace annealing. The effective dielectric constant of k/spl sim/9.4 and equivalent oxide thickness of 26 /spl Aring/ are produced, and the interfacial layer and carbon clusters are not observed in this paper. The electrical responses of MOS capacitor under heating and illumination are used to identify the conduction mechanisms. For the positively biased case, the conduction mechanism is shown to be dominated by Schottky emission with an effective barrier height of 1.12/spl plusmn/0.13 eV. For the negatively biased case, the gate current is shown to be due to the generation-recombination process in depletion region and limited by the minority carrier generation rate. The feasibility of integrating alternative gate dielectric on SiC by a low thermal budget process is demonstrated.     

Thermally robust HfN metal as a promising gate electrode for advanced MOS device applications

A systematic study of thermally robust HfN metal gate on conventional SiO/sub 2/ and HfO/sub 2/ high-/spl kappa/ dielectrics for advanced CMOS applications is presented. Both HfN-SiO/sub 2/ and HfN-HfO/sub 2/ gate stacks demonstrates robust resistance against high-temperature rapid thermal annealing (RTA) treatments (up to 1000/spl deg/C), in terms of thermal stability of equivalent oxide thickness (EOT), work function, and leakage current. This excellent property is attributed to the superior oxygen diffusion barrier of HfN as well as the chemical stability of HfN-HfO/sub 2/ and HfN-SiO/sub 2/ interfaces. For both gate dielectrics, HfN metal shows an effective mid-gap work function. Furthermore, the EOT of HfN-HfO/sub 2/ gate stack has been successfully scaled down to less than 10 /spl Aring/ with excellent leakage, boron penetration immunity, and long-term reliability even after 1000/spl deg/C annealing, without using surface nitridation prior to HfO/sub 2/ deposition. As a result, the mobility is improved significantly in MOSFETs with HfN-HfO/sub 2/ gate stack. These results suggest that HfN metal electrode is an ideal candidate for ultrathin body fully depleted silicon-on-insulator (SOI) and symmetric double-gate MOS devices.     

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Thermally stable, high-quality ultrathin (EOT=13 A) CVD HfAlO gate dielectrics with poly-Si gate electrode have been investigated for the first time. Results demonstrate that while in situ doping with Al significantly increases the crystallization temperature of HfO/sub 2/ up to 900/spl deg/C and improves its thermal stability, it also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation. The effects of Al concentration on crystallization temperature, fixed oxide charge density, and mobility degradation in HfAlO have been characterized and correlated.     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²     

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.     

Co-optimization of the metal gate/high-k stack to achieve high-field mobility >90% of SiO/sub 2/ universal mobility with an EOT=/spl sim/1 nm

HfO/sub 2/ and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO/sub 2/ universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-/spl kappa/ dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO/sub 2/ and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO/sub 2/ gate stack.     

Impact of metal work function on memory properties of charge-trap flash memory devices using fowler-nordheim P/E mode

This letter reports the impact of metal work function (/spl Phi//sub M/) on memory properties of charge-trap-Flash memory devices using Fowler-Nordheim program/erase mode. For eliminating electron back tunneling and hole back tunneling through the blocking oxide during an program/erase operation, a gate with /spl Phi//sub M/ of 5.1-5.7 eV on an Al/sub 2/O/sub 3/-SiN-SiO/sub 2/ (ANO) stack is necessary. Compared to a thickness optimized n/sup +/ poly-Si/ONO stack, a high-work-function gate on an ANO stack shows dramatic improvements in retention versus minimum erase state.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.     

Quality improvement of ultrathin gate oxide by using thermal growth followed by SF ANO technique

Rapid thermal oxide followed by anodization in direct current superimposed with scanning frequency alternating current was demonstrated for the first time to have an improved quality in ultrathin gate oxides. Compared with the thermal oxide grown without the scanning-frequency anodization (SF ANO) treatment, the gate leakage current density (J/sub g/) of SF ANO sample is significantly reduced without increasing the thickness of gate oxide. In addition, it could be observed that the interface trap density (D/sub it/) is reduced with tighter distribution. It is suggested that the bulk traps and interface traps in thermally grown oxide can be repaired during the SF ANO process.     

Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric

This investigation is the first to demonstrate a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si (LTPS) thin film transistors (TFTs), composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O-plasma. The stack oxide shows a very high electrical breakdown field of 8.4 MV/cm, which is approximately 3 MV/cm larger than traditional PECVD TEOS oxide. The field effective mobility of stack oxide LTPS TFTs is over 4 times than that of traditional TEOS oxide LTPS TFTs. These improvements are attributed to the high quality N/sub 2/O-plasma grown ultrathin oxynitride forming strong Si/spl equiv/N bonds, as well as to reduce the trap density in the oxynitride/poly-Si interface.     

堆叠栅介质MOS器件栅极漏电流的计算模型

采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。     

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.