Speed optimization of edge-triggered CMOS circuits for gigahertzsingle-phase clocks

In digital circuits, a transistor connected to a particular circuit node does not always load that node by a gate capacitance proportional to C_oxWL if the transistors connected to its source are turned off. Such an observation, illustrated in this paper by a detailed analysis of the Yuan-Svensson D-flip-flop (D-FF) can be used to advantage both in sizing the transistors and in developing better configurations. A glitch-free, general purpose, and faster D-FF is presented here which has complementary outputs and runs at frequencies from tens of hertz to a couple of gigahertz for a 1-μm CMOS technology. Measured maximum clock frequency of a divide-by-16 circuit is 2.65 GHz at 5 V supply, whereas that of a dual-modulus frequency prescaler, dividing by 64/65, goes up to 1.6 GHz at 5 V     

Digital integrated circuit using integrated InAlAs/InGaAs/InP HEMTsand InAs/AlSb/GaSb RITDs

The demonstration of the first integrated circuit using monolithically integrated InAs/AlSb/GaSb resonant interband tunnelling diodes (RITDs) and InAlAs/InGaAs/InP high electron mobility transistors (HEMTs) is reported. A D-flip-flop (D-FF) was implemented using the monostable/bistable logic element (MOBILE) circuit architecture, with a measured effective voltage gain in excess of 380. Power dissipation of less than 2.8 mW/gate was measured     

A 40-GHz D-type flip-flop using AlGaAs/GaAs HBT's

We report master-slave D-type flip-flop (D-FF) circuit implemented with AlGaAs/GaAs HBT's. The fabricated HBT's had an f_T of 107 GHz and an f_max of 110 GHz. To maximize the speed, the logic swing and transistor size in the IC were optimized. In the D-FF, to facilitate the high-speed testing, a selector circuit was integrated on the same chip. As a result, the operation of this IC was confirmed up to 40 GHz, which is the highest speed in D-FF     

A 80-gbit/s D-type flip-flop circuit using InP HEMT technology

80-Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology, which has a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. The circuit was designed with differential operation based on source-coupled FET logic (SCFL). To overcome deterioration of the 80-GHz clock signals in a single-ended to differential signal converter in the input buffer, a rat-race circuit was used as a converter. Measurements showed that the circuit achieved a gain of over 2 dB higher than a conventional converter using a differential pair circuit, and power consumption was reduced from 380 to 260 mW. The power supply voltage was -5.7 V, and total power consumption was 1.2 W. Since there is no commercially available 80-Gbit/s-pulse pattern generator, we developed a selector module to measure the D-FF. These measurements showed that the D-FF successfully operated at 80 Gbit/s, which is almost twice the speed reported to date.     

A 15-GHz monolithic two-modulus prescaler

A high-speed two-modulus prescaler for divide-by-4/5 select was successfully realized adopting a new circuit design that reduces the effective fan-out of each D-flip-flop (D-FF) to one. To assure stable and high-speed operation, a low-voltage signal amplitude of 250 mV in the D-FF was adopted for both true-and-complementary and single-phase signals. Using a 70-GHz-f_T GaAs/AlGaAs HBT technology, the D-FF operated stably up to 18.6 Gb/s at designed bias voltages of 9 V with power dissipation of 0.55 W, and the prescaler operated up to 15.5 GHz with power dissipation of 1.5 W     

Defect Tolerance Based on Coding and Series Replication in Transistor-Logic Demultiplexer Circuits

We present a family of defect tolerant transistor-logic demultiplexer circuits that can defend against both stuck-ON (short defect) and stuck-OFF (open defect) transistors. Short defects are handled by having two or more transistors in series in the circuit, controlled by the same signal. Open defects are handled by having two or more parallel branches in the circuit, controlled by the same signals, or more efficiently, by using a transistor-replication method based on coding theory. These circuits are evaluated, in comparison with an unprotected demultiplexer circuit, by: 1) modeling each circuit's ability to tolerate defects and 2) calculating the cost of the defect tolerance as each circuit's redundancy factor R, which is the relative number of transistors required by the circuit. The defect-tolerance model takes the form of a function giving the failure probability of the entire demultiplexer circuit as a function of the defect probabilities of its component transistors, for both defect types. With the advent of defect tolerance as a new design goal for the circuit designer, this new form of performance analysis has become necessary.     

A 250-Mb/s, 700-mW, 32-highway×8-b S/P converter LSI withcross-access memory

A multihighway serial/parallel (S/P) converted LSI chip suitable for the broadband Integrated Services Digital Network (B-ISDN) node interface is presented. The chip, fabricated with 0.8-μm BiCMOS technology, handles 32-highway×8 b of S/P, P/S conversion at up to 250 Mb/s and has a power dissipation of 700 mW. The chip features cross-access memory and a current-cut-type CMOS/ECL interface circuit. Each of these features is described and evaluated. A newly developed BiNMOS-type D-flip-flop (D-FF) is used to speed up the cross-access memory and is compared to a CMOS D-FF     

A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage

This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V_dd², decreasing the supply voltage yields a large reduction in power consumption. The main design objectives for these circuits are glitch-free operation and low power consumption at low supply voltage. The proposed D-FF circuit has been compared with previously known circuits and has been shown to provide superior performance. All circuits in this paper have been simulated using HSPICE with a 0.4-μm CMOS technology at a 2-V supply voltage. An analysis of a serial pipeline multiplier design establishes the superiority of the proposed circuit in that application.     

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。     

A Method of Transformation from Symbolic Transfer Function to Active-RC Circuit by Admittance Matrix Expansion

Active-RC circuits containing 2-terminal linear passive elements and ideal transistors or operational amplifiers are derived from symbolic voltage or current transfer functions by admittance matrix transformations without any prior assumption concerning circuit architecture or topology. Since the method is a reversal of symbolic circuit analysis by Gaussian elimination applied to a circuit nodal admittance matrix, it can generate all circuits using the specified elements that possess a given symbolic transfer function. The method is useful for synthesis of low-order circuits, such as those used for cascade implementation, for deriving alternative circuits with the same transfer function as an existing circuit or for realizing unusual transfer functions, as may arise, for example, where a transfer function is required that contains specific tuning parameters     

Grounded capacitance multipliers based on active elements

In this study, we present two new grounded capacitance multiplier circuits based on a negative-type second-generation current conveyor (CCII-) and an inverting second-generation current conveyor (ICCII). The first proposed circuit consists of one CCII- and a voltage follower (VF) employing two NMOS transistors while the second proposed circuit is composed of an ICCII and an inverting voltage follower (IVF) including two NMOS transistors. Each circuit contains two resistors, and single grounded capacitor, which is attractive for integrated circuit realization. No active and passive component matching conditions are required for the realization of the proposed capacitance multiplier circuits. The simulation results are included to confirm the theory.     

An 80-Gb/s optoelectronic delayed flip-flop IC using resonanttunneling diodes and uni-traveling-carrier photodiode

This paper describes an 80-Gb/s optoelectronic delayed flip-flop (D-FF) IC that uses resonant tunneling diodes (RTDs) and a uni-traveling-carrier photodiode (UTC-PD). A circuit design that considers the AC currents passing through RTDs and UTC-PD is key to boosting circuit operation speed. A monolithically fabricated IC operated at 80 Gb/s with a low power dissipation of 7.68 mW. The operation speed of 80 Gb/s is the highest among all reported flip-flops. To clarify the maximum operation speed, we analyze the factors limiting circuit speed. Although the bandwidth of UTC-PD limits the maximum speed of operation to 80 Gb/s at present, the circuit has the potential to offer 100-Gb/s-class operation     

Reliability for nanomagnetic logic (NML) readout circuit under single event effect

In the application for the space radiation environment, NML circuits face a reliability challenge mainly from their CMOS peripheral circuits, suffering from single event effects (SEE). An on-chip readout interface circuit (RIC) for NML circuit is designed based on dual-barrier magnetic tunnel junction (DB-MTJ). The sensitive nodes to SEE in RIC are analyzed. The SEU required critical charge in RIC is described. The impacts of energetic particle hitting time and technology node on the critical charge are studied. As the technology node scales down, the critical charge will significantly decrease. Two efficient hardening technologies for RIC are presented: local transistors׳ size and symmetrical load capacitances. By increasing local transistors׳ size or decreasing the load capacitance, the critical charge will be improved, which enhances the immunity to SEE.     

High-speed high-precision CMOS analog rank order filter with O(n) complexity

A continuous-time implementation of a voltage-mode analog rank order filter is presented. The proposed circuit features high speed, high precision, and simple circuit implementation. The overall architecture exhibits linear increase of complexity with the number of inputs (O(n)), at the rate of seven transistors per input. Rank is easily programmable with the tail current for all rank order values from the Max to the Min case, and the programmed function is accurate for a wide range of tail currents. Moreover, unlike previously reported rank order structures the precision of the proposed circuit does not rely on perfect matching of all input transistors. Simulations as well as experimental results are presented that verify the functionality and performance of the proposed circuit.     

Indirect Programming of Floating-Gate Transistors

Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG programming techniques require disconnection of the transistor from the rest of its circuit while it is being programmed. We present a new method of programming FG transistors that does not require this disconnection. In this indirect programming method, two transistors share a FG allowing one to exist directly in a circuit while the other is reserved for programming. Since the transistor does not need to be disconnected from the circuit to program it, the switch count is reduced, resulting in fewer parasitics and better overall performance. Additionally, the use of these indirectly programmed FG transistors allows a circuit to be tuned such that the effects of device mismatch are negated. Finally, the concept of run-time programming is introduced which allows a circuit to be recalibrated while it is still operating within its system     

RFCMOS Unit Width Optimization Technique

In this paper, we demonstrate a unit width ( W_f) optimization technique based on their unity short-circuit current gain frequency (f_T) unilateral power gain frequency (f_MAX)? and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the W_f change is different; hence, some tradeoff is required to obtain the optimum W_f value. During the HF noise analysis, a new FOM is proposed to study the W_f effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in W_f does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor's layout and helps to select the optimum Wf for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit's performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum W_f for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.     

Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing

A new CMOS current-mode pseudo-exponential circuit based on the n-order Taylor series expansion will be presented. The most important advantage of the circuit with respect to the previously reported similar ones is the smaller value of the total computing error (under 0.3 dB), for a maximal output range of the proposed function generator greater than 40 dB. The total error could be very easily reduced by increasing the number of terms considered in the Taylor expansion. The circuit also presents the advantage of the independence of the output current on technological parameters. The frequency response is improved due to the strong inversion operation of all MOS transistors and to the current-mode operation of the circuit. The circuit area is relatively small due to the exclusively utilization of MOS transistors. The SPICE simulations confirm the theoretical estimated results. The proposed exponential function generator is designed in 0.12-mum CMOS technology and it consumes a reasonable power (less than 0.3 mW) for obtaining the previous mentioned computing error and has a low-voltage operation (a minimal accepted supply voltage under 1.2 V). The total silicon occupied area of the exponential function generator with third-order approximation is about 5.9 mum times 7.9 mum.     

Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays

High-throughput electrode arrays are required for advancing devices for testing the effect of drugs on cellular function. In this paper, we present design criteria for a potentiostat circuit that is capable of measuring transient amperometric oxidation currents at the surface of an electrode with submillisecond time resolution and picoampere current resolution. The potentiostat is a regulated cascode stage in which a high-gain amplifier maintains the electrode voltage through a negative feedback loop. The potentiostat uses a new shared amplifier structure in which all of the amplifiers in a given row of detectors share a common half circuit permitting us to use fewer transistors per detector. We also present measurements from a test chip that was fabricated in a 0.5-mum, 5-V CMOS process through MOSIS. Each detector occupied a layout area of 35 mumtimes15 mum and contained eight transistors and a 50-fF integrating capacitor. The rms current noise at 2-kHz bandwidth is ap110 fA. The maximum charge storage capacity at 2 kHz is 1.26times10⁶ electrons