A two-phase shift register using Si tunnel MIS switching diodes

A novel monolithic shift register consisting of tunnel MIS switching diode arrays is proposed, in which gold and molybdenum electrodes overlapping in part are arranged in close vicinity on thin oxides formed on an n on p⁺silicon epitaxial wafer. Directional shift with two-phase clocks is achieved by making use of unsymmetric electrode configurations and current coupling effects between adjacent elements together with the difference in the sustain voltages of ON states between the two metals. Both ten and twenty-bit devices have functioned as designed. The margins in the driving conditions depend on the unsymmetry in the electrodes. The maximum operation frequency of 3 MHz has been attained which is limited by the CR time constant. The proposed register can be realized with very simple fabrication processes which involve no impurity diffusion.     

A low-latency asynchronous shift register

In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.     

A bipolar four-phase dynamic shift register

A 512-b dynamic shift register is integrated on 6.4-mm/SUP 2/ active chip area. The frequency range is from 100 Hz to 3 MHz. At 1 MHz the power dissipation is 20 mW. The performance of the shift register is insensitive to spread in process parameters because the information is regenerated in each cell. The comparison of the measured and the calculated working range shows the essential influence of all parasitic capacitances.     

A two-phase plasma-coupled static shift register

In designing an experimental 2-bit plasma-coupled shift register, fabricated with standard bipolar technology, it is shown that a simplification of the existing plasma-coupled device (PCD) concept by omission of the double base diode not only decreases the power dissipation and increases the ease of fabrication, but also increases the attractive simplicity of the basic cell. The average power dissipation of the new device is 200 /spl mu/W/bit at a clock frequency of 3 MHz. The bit density is 135 bit/mm/SUP 2/ with 10-/spl mu/m spacing between interconnection lines 10 /spl mu/m in width. A hypothetical layout with dielectric isolation and closer tolerances results in a bit density of 900 bit/mm/SUP 2/ and an estimated power dissipation of 80 /spl mu/W/bit.     

A CCD serial to parallel shift register

Charge-coupled devices have been well known for their serial-type applications. The authors report a new scheme whereby parallel outputs can be obtained from every bit of a serial CCD shift register without destroying the transferred charge and without the use of an external resetting pulse. The results of a 20-b 3/spl phi/ CCD shift register with parallel outputs are described. The work extends the applicability of CCD's to a less restricted area.     

A surface-charge shift register with digital refresh

A digital shift register using the surface-charge transistor structure in which adjacent rows propagate in opposite directions and which has refresh turn-around circuits at the ends of each row is described. Two process compatible refresh circuits requiring only four times the basic bit storage area have been designed, and a test circuit composed of two 16-bit shift registers that propagate in opposite directions and are connected by these circuits has been built and tested. The regeneration characteristics of these refresh circuits have been measured as a function of transfer time in both the complete and partial transfer modes (`fat zero'). Operation of one of these 32-stage shift registers and its refresh at 10 MHz is presented.     

一种容错可逆的通用移位寄存器设计

为了使计算系统具有低功耗和容错能力,基于可逆逻辑设计了一种容错的通用移位寄存器。提出了一种新型的容错可逆逻辑门(Parity-Preserving D Flip_flop Gate, PP_DFG),利用它和存在的容错门,完成了寄存器和多路数据选择器的设计。综合上述模块,构建了容错可逆的通用移位寄存器电路,用Verilog 硬件描述语言建模,仿真显示电路逻辑结构正确。同现有电路相比,根据量子代价、延迟和无用输出对其进行性能评估,结果表明该电路不仅具有容错功能,而且性能提高了16%~50%。设计的电路可作为一种重要的存储元件应用于未来的低功耗计算系统。     

A shift register architecture for high-speed data sorting

This paper presents a shift-register architecture or SRA, for data sorting applications. The operations performed by the proposed architecture are (1)shift right, (2)shift left, (3)load, and (4)initialize. Sorting operations, such as insert and delete, can be realized by the combination of these 4 basic operations. The architecture is very regular and mainly composed of two basic cells,sort-cell and compare-cell. The latter is designed to generate control signals orchestrating the operation of sort cells which contain the sorted input sequences. Experimental results show that a single chip solution can achieve real-time performance based on 1.2m CMOS double-metal technology.Work support by the National Science Council of Taiwan, ROC under grant NSC82-0404-E009-184.     

A new static shift register with dynamic transfer

A new shift register of extremely low d.c. standby power has been implemented in a simplified bipolar transistor technology using 4 mask steps up to metallization and 2 diffusions only. The bit density is 250 bit/mm² with 5 μm line dimensions, the standby power 0·1 μW/bit and the cycle time 150 nsec at 150 μW/bit. The shift register features a new operation principle: In standby, it is truly static, whereas for shifting the memory operates dynamically utilizing the effect that a dynamically unbalanced flip-flop switches into a definite state. The dynamic charge unsymmetry originates from the state of the previous cell and is shifted to the next one after each clock cycle.     

互控?钟控移位寄存器序列

提出了一种新的互控钟控移位寄存器模型.该模型具有设备简单,易于实现,并且产生的序列周期长,线性复杂度高,抗攻击能力强等特点.这种模型被进一步改进,利用它可以生成更好的序列.     

A two-phase drive bipolar linear image sensor using zigzag arrangement of PCD shift register elements

A bipolar linear image sensor composed of a 512-bit photodiode array, two 256-bit switch arrays and two 512-bit plasma-coupled device (PCD) shift registers characterized by zigzag arrangement of conductance transistors has been developed. As compared with a conventional PCD image sensor which needs four-phase or six-phase shift pulses to drive the PCD shift registers, the newly developed sensor requires only two-phase shift pulses and greatly simplifies an external driving circuit. In addition, it can be fabricated by using only four photomasks, providing good cost performance.     

The bipolar transistor bucket-brigade shift register

An analysis of the bipolar transistor bucket-brigade shift-register operation is presented for comparison to other charge-transfer shift-register schemes. It is shown that incomplete charge transfer, the most important performance limiting effect for the charge-coupled device and the IGFET bucket brigade, is very small under most practical operating conditions for the bipolar transistor bucket brigade. In addition to charge loss due to finite transistor current gain h/SUB fe/ the next most important performance limitation comes from collector-emitter capacitance. It is shown that this collector-emitter capacitance leads to reduced analog time delay on transfer through the register and to signal attenuation effects similar to those resulting from incomplete charge transfer. Using the results of the analysis, experimental data reported by Sangster are discussed and a comparison of the advantages and disadvantages of the bipolar bucket-brigade register with the MOS charge-transfer registers is made.     

A 20-MHz p-n-p-n shift register with current mirror coupling

An experimental 4-bit static two-phase shift register is described which uses p-n-p-n switches as bistable elements. A new current mirror coupling between these elements has two advantages. 1) The turnoff of the slow p-n-p-n switches occurs in two clock phases. This results in a high clock frequency of 20 MHz at low average power dissipation of 200 /spl mu/W/bit. 2) A very compact cell design is possible, resulting in a high bit density of 80 bit/mm/SUP 2/ with a standard bipolar process and conservative layout rules. The limiting values of the clock-pulse voltages are measured and discussed in qualitative terms.     

A 512-bit shift register using compact two-phase single fluxquantum clock generators with large margins and low power

A 512-b shift register was built and tested up to 14.5 GHz. The shift register uses a two-phase clock which is generated by coupling a master control line over many asymmetrically biased two-junction SQUIDs. Compared with other shift registers with Josephson transmission lines to deliver clock, this new clock system provides short delay, low power dissipation, and large DC bias margins. The shift register uses about 3000 Nb/AlO_x/Nb Josephson junctions and consumes about 0.1 mW     

A V-groove oxide isolated bipolar bucket brigade shift register

A V-groove oxide isolated bipolar bucket brigade shift register structure is described in this paper. The operation of the shift register is analyzed to determine the frequency and transfer efficiency limitation and point out the inherent advantages of such a structure. Measurements carried out on experimental 36-stage V-groove BBD registers are presented to demonstrate the capabilities of the devices. The proposed V-groove BBD structure results in registers with higher operating frequencies and greatly increased packing density when compared to standard junction isolated devices. These improvements are obtained without sacrificing the low or mid-frequency response and make these devices useful in video delay line applications.     

Design and testing of data-driven self-timed RSFQ shift register

We report design, implementation and testing of a superconductive rapid single flux quantum (RSFQ) shift register based on a data-driven self-timed (DDST) architecture, and demonstrated the validity of this asynchronous design approach. In the DDST architecture, a clock signal is localized within the basic modules, and complementary data signals are used between the modules to transmit timing information. A larger system is simply an array of the basic modules and no extra timing consideration is required. Monte Carlo analysis on a 4-bit DDST shift register has shown that a 40-kbit shift register operating at 20 GHz can be built by using the present Nb Josephson technology. We have observed fully correct operation of a cascade of two 4-bit DDST shift registers with dc bias voltage margin of ±15% at low frequency and ±10% at 20 GHz.     

A dual-differential analog shift register with a charge-splitting input and on-chip peripheral circuits

A very high degree of stability and the elimination of external support circuitry are requirements for many signal-processing applications of analog charge-coupled devices. A device that meets these requirements has been designed and fabricated. The device requires a single clock input signal and achieves a gain-temperature stability of /spl plusmn/0.015 dB over 0-50/spl deg/C and a gain-voltage stability of /spl plusmn/0.05 dB over a power-supply variation of /spl plusmn/10 percent. The NMOS device demonstrates the compatibility of digital, linear, and charge-coupled devices on a single chip.     

Amorphous silicon shift register for addressing output drivers

An amorphous silicon (a-Si) shift register is described. By integrating this shift register design with an array of a-Si drivers, the cost/complexity of the interface to the array is significantly reduced, without trading off speed. Circuit design considerations unique to a-Si devices are also discussed along with their processing