Self-firing cell scheduler for input queueing ATM switches

The authors propose a simple cell scheduler for input queueing ATM switches. The proposed self-firing cell scheduler consists of N² processing elements connected by a two dimensional torus network, where each processing element can determine the diagonal by itself in a distributed manner. It allows a simple implementation for high speed ATM switches     

Analysis of input and output queueing for nonblocking ATM switches

A switch model for ATM networks is analyzed. Its interconnection network is internally nonblocking and is provided with dedicated input and output queues, one per switch inlet and one per switch outlet. The switch operates with an internal speed-up: more than one packet per slot can be transferred from the head-of-line positions of the input queues to each output queue by the interconnection network. Two different operation modes are considered for the interaction between input and output queues: backpressure mode and queue loss mode. The analytical model developed for the evaluation of the switch performance under random traffic assumes an infinite size for the switch, arbitrary values for input and output queue size, as well as for the speed-up factor. Switch throughput, packet delay and loss performance are evaluated and the analytical model accuracy is assessed using computer simulation results     

An efficient contention resolution algorithm for input queuing atm cross-connect switches

This paper describes an efficient contention resolution algorithm and its distributed implementation for large capacity input queuing cross-connect switches, which will establish virtual paths in future broadband ATM networks. The algorithm dynamically allocates sending time to cells held in input queues when no contention is indicated in the designated output ports. An expression for the mean delay and the cell loss probability for random traffic are derived through an approximate analysis. Input cells are served on a first-come, first-served basis as conventional contention resolution algorithms whose throughput saturates at 58 per cent because of head of line blocking in input queues. The proposed algorithm achieves a maximum throughput of 76 per cent.     

Optimum architecture for input queuing ATM switches

An input queueing ATM switch architecture employing the contention resolution called 'scheduling algorithm' is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.<>     

Reservation-based contention resolution mechanism forBatcher-Banyan packet switches

The authors introduce a new method, called ring reservation, to design high-capacity packet switches. Input buffering is used with output port reservations to eliminate packet collisions. They describe a 32×32 prototype packet switch, built as a part of a broadband ISDN prototype, which has a per-port capacity of 30-55 Mbit/s     

Optical contention resolution and buffering module for ATM networks

A new type of buffering module is introduced, suitable for incorporation into optical switch fabrics handling ATM cells. It comprises 2*2 optical switches and optical delay lines, and is equivalent to two interlinked buffers. Performance is characterised in terms of attenuation, crosstalk and cell loss.<>     

高速光交换机竞争解决机制研究

在光分组交换网络中,当同一时刻有两个或两个以上的分组以同一波长从同一端口离开光交换节点时就会出现分组竞争,采用不同的竞争解决方法对光分组交换网络性能会产生巨大影响.在光分组交换中解决竞争主要有光缓存、波长变换、偏射路由三种方式.详细阐述了这三种竞争解决方法的原理、实现方式及特点,并对今后发展趋势做出展望.     

Accurate modelling of the queueing behaviour of shared buffer ATM switches

A model for the analysis of multistage switches based on shared buffer switching for Asynchronous Transfer Mode (ATM) networks is developed, and the results are compared with the simulation. Switches constructed from shared buffer switches do not suffer from the head of line blocking which is the common problem in simple input buffering. The analysis models the state of the entire switch and extends the model introduced by Turner to global flow control with backpressure mechanism. It is shown that buffer utilization is better and throughput improves significantly compared with the same switch using local flow control policy. Copyright © 1999 John Wiley & Sons, Ltd.     

FIRM: high-speed distributed scheduling for ATM switches withmultiple input queues

A new distributed scheduling algorithm for advanced input queueing switch architectures called FIRM is introduced. FIRM provides improved performance characteristics at high load compared to the most efficient alternative, improved fairness, and tighter service guarantees     

Analysis of nonblocking ATM switches with multiple input queues

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation     

A queueing model for an ATM rate control scheme

Many applications in telecommunications engineering lead to highly degenerate partitioned Markov chains of QBD type. In this paper, we study a traffic shaping scheme which is based on a generalization of the bucket method. The arrival process is modeled by a discrete Markovian arrival process. For this model, a detailed mathematical analysis leads to special algorithms involving matrices of lower order. The characteristics of the model are discussed from this viewpoint. Some performance measurements are derived and numerical examples are shown to demonstrate the effectiveness of the rate control scheme.This research was supported in part by Grant No. DDM-8915235 from the National Science Foundation.     

Throughput analysis for input-buffered ATM switches with multipleFIFO queues per input port

Using two different packet scheduling policies, the maximum throughputs of an input-buffered ATM switch with m-FIFO queues per input port are derived when the switch size is large     

Speedup and buffer division in input/output queuing ATM switches

The capacity of a switch is built out of two factors: space parallelism and speedup. A switch has space parallelism if more than one input port can transmit simultaneously. Speedup is the ratio of the switch's internal link speed over the incoming link speed. An input-queuing switch uses only the first factor (space parallelism), and a share-medium or a share-memory output queuing switch uses only the second factor (speedup). However, to build a large switch, both factors are normally used. A large switch's capacity can be built with less space parallelism (the space factor), but more speedup (the time factor), or vise versa. Buffers are needed at both the input and the output ports. In this paper, we show how to divide the buffers between the input and the output queues and how the optimal division is affected by the (space, time) combinations.     

Credit-based fair queueing for ATM networks

A simple and practically attractive rate-based scheduling algorithm for ATM networks is presented. By using simple counters to keep track of the transmission credits earned by each traffic stream, the algorithm decides which stream to serve next, based on their bandwidth shares and the values of the counters     

Head of the line arbitration of packet switches with combined input and output queueing

A single-stage non-blocking N × N packet switch is considered. Data units may be stored before switching at the inputs as well as after switching at the outputs. Some output buffering capacity is intended to achieve high throughput, whereas an additional input buffering capacity keeps losses due to input-buffer overflow reasonably low. The paper studies the impact on performance of the head of the line arbitration policy, i.e. the sequence which is used to transfer data units from the heads of input queues to each output queue. The investigation is based on two performance measures: the average delay and the maximum throughput of the switch. Closed-form expressions for the FCFS, LCFS and the ROS policies are obtained. The result of the average delay with the FCFS policy leads to a lower bound, and that with the LCFS policy to an upper bound for the average delay, corresponding to an arbitrary symmetric policy which does not use information related to the state of the input queues. It is shown that the maximum throughput does not depend on the head of the line arbitration policy. It depends only on the output-buffer size and the packet-size distribution. The cases of fixed and exponentially distributed packet sizes are studied. The effects of asymmetric policies which result in different behaviours of some of the input queues is also considered.     

Write policies for multicast ATM switches

A unicast and multicast-pushout write policy for shared-memory ATM switches is proposed. The scheme allocates buffers based on the service rates of unicast and multicast cells to ensure that maximum throughput can be maintained     

Reminder on queueing theory for ATM networks

Queueing theory is a very useful means for performance prediction during the system design phase, for resource dimensioning and for planning of networks according to load andquality of service figures. In this paper, an overview is given about traffic models for ATM traffic sources, generic ATM traffic control models and performance evaluation methods.     

Provisioning QoS features for input-queued ATM switches

A new scheduling algorithm is proposed to improve on existing algorithms designed for input-queued ATM switches. By assigning a session weight according to its queue length normalised by its rate and using maximum weight matching to obtain a match, the proposed algorithm can avoid starvation of slow sessions, thus providing good delay properties as well as fair services, and at the same time reducing traffic burstiness     

An efficient architecture for fault-tolerant ATM switches

A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand     

Fault-tolerant multicasting in MINs for ATM switches

This article proposes a fault-tolerant multicast routing algorithm in multistage interconnection networks (MINs) for ATM switch architectures. It employs both region and cube encoding schemes as the header encoding scheme. A multicast packet can be routed to its destinations in only two phases through the MIN having a single faulty element