Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation

In this work, a simple architecture of a precision CMOS multi-input current comparator is proposed. The circuit is based on the usage of a multi-input current Max circuit. The inherent corner error of the Max circuit is eliminated, using a feedback circuit, increasing thus the precision of the comparator. Only the digital output corresponding to the maximum (or minimum) input current is at logic 1, while the other outputs are at logic 0. An application of the comparator to the analog implementation of a current-mode median filter is also presented. A five-input comparator and a three-input median filter were fabricated using double-poly double-metal 2 m CMOS MIETEC technology. Experimental results are given, to validate the theoretical analysis and to demonstrate the feasibility and the precision of the proposed circuits.     

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm² test chip with the super H architecture using 0.35-m four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.     

Design of a window comparator with adaptive error threshold for online testing applications

This paper presents a novel window comparator circuit whose error threshold adjusts adaptively with respect to its input signal levels. Advantages of adaptive error thresholds over constant or relative error thresholds in analog testing applications are discussed. Analytical equations for guiding the design of the comparator circuitry are derived. The proposed comparator circuit has been designed and fabricated using a CMOS technology. Measurement results of the fabricated chip are presented.     

一种新型的高性能CMOS电流比较器电路

分析了目前几种高性能连续时间CMOS电流比较器的优缺点,提出了一种新型CMOS电流比较器电路．它包含一组具有负反馈电阻的CMOS互补放大器、两组电阻负载放大器和两组CMOS反相器．由于CMOS互补放大器的负反馈电阻降低了它的输入、输出阻抗,从而使电压的变化幅度减小,所以该电流比较器具有较短的瞬态响应时间和较快的速度．电阻负载放大器的使用减小了电路的功耗．利用1.2μm CMOS工艺HSPICE模型参数对该电流比较器的性能进行了模拟,结果表明该电路的瞬态响应时间达到目前最快的CMOS电流比较器的水平,而功耗则低于这些比较器,具有最大的速度/功耗比．此外,该CMOS电流比较器结构简单,性能受工艺偏差的影响小,适合应用于高速/低功耗电流型集成电路中．     

A/D转换器中的CMOS自稳零电压比较器的设计

本文介绍了一种CMOS自稳零电压比较器的设计。该比较器具有高精度,高灵敏度和较快的速度,其工艺条件及参数与数字电路兼容。文章通过电路设计特点说明其工作原理。对其中的差值电路的设计,特别是放大器的设计,作了具体分析。该比较器完全满足了CM0808八位A/D转换器的要求。     

150Ms/s、6bit CMOS数字工艺折叠、电流插值A/D转换器

在1.2μm SPDM标准数字CMOS工艺条件下,实现6bit CMOS折叠、电流插值A/D转换器;提出高速度再生型电流比较器的改进结构,使A/D转换器(ADC)总功耗下降近30%;提出一种逻辑简单易于扩展的解码电路,以多米诺(Domino)逻辑实现.整个ADC电路中只使用单一时钟.在5V电压条件下,仿真结果为采样频率150-Ms/s时功耗小于185mW,输入模拟信号和二进制输出码之间延迟小于2个时钟周期.     

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture

This paper describes a high-speed, low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with a built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with a body-bias control circuit is employed to reduce distortion at a high sampling rate. Moreover, a $V_{rm TH}$ generator using a replica of the original comparator is also proposed to compensate for $V_{rm TH}$ deviation due to the process variations. A test chip was fabricated using 90-nm CMOS technology, and showed a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.      

The Concept of Operational Rank Extractor

An operational rank extractor (ORE) is introduced in this paper as an operational amplifier having rank extractors at its inputs. This versatile building block can implement a variety of nonlinear transfer functions such as a dead-zone amplifier, a limiter, a full-wave rectifier, and a tri-state comparator (including hysteretic behavior). A 6-input circuit has been implemented in a 2 m CMOS process. The total silicon area is 460 × 100m², and the circuit dissipates 0.7 mW from a single 5 V supply. Various circuit configurations are analyzed theoretically, and experimental results are also provided.     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW     

Fully Differential CMOS Current Feedback Operational Amplifier

This paper presents a new CMOS fully differential current feedback operational amplifier (FDCFOA). The proposed CMOS realization of the FDCFOA is based on a novel class AB fully differential buffer circuit. Besides the proposed FDCFOA circuit is operating at supply voltages of ±1.5 V, it has a total standby current of 400 A. The applications of the FDCFOA to realize variable gain amplifier, fully differential integrator, and fourth order fully differential maximally flat low pass filter are given. The fourth order filter provides 8 dB gain and a bandwidth of 4.3 MHz to accommodate the wideband CDMA standard. The proposed FDCFOA and its applications are simulated using CMOS 0.35 m technology.Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include low voltage analog CMOS circuit design, filtering and applications suitable for VLSI.Inas Awad was born in Cairo, Egypt, in 1971. She received the Bachelor, the M.Sc. and the Ph.D. degrees in Electronics and Communications from Cairo University in 1994, 1997 and 2000, respectively. In 1995, she joined the department of Electronics and Communications, Cairo University, Fayoum-Campus as a teaching assistant and now she is an Assistant Professor at the same department. Her primary research interest is in analog circuits with particular emphasis on current-mode approach and low-voltage low-power CMOS designs.     

An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique

This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6 m CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.     

一种带增益提高技术的高增益CMOS运算放大器的设计

给出了一种用在高速高精度流水线型模数转换器中的具有高增益和高单位增益频率的全差动CMOS运算放大器的设计,电路结构主要采用折叠式共源共栅结构,并采用增益提高技术提高放大器的增益。共模反馈电路由开关电容共模反馈电路实现。模拟结果显示,其开环直流增益可达到106 dB,在负载电容为2 pF时单位增益频率达到了167 MHz,满足了对模数转换器的高速度和高精度的要求。     

Experimental implementation of $$\Delta \Sigma $$AD modulator with dynamic analog components

This paper presents an experimental prototype of 2nd-order multi-bit \(\Delta \Sigma \)AD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feed-forward modulator is realized by a passive-adder embedded successive approximation register analog to digital converter which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a pre-amplifier is not used. Proposed modulator is fabricated in TSMC 90 nm CMOS technology. Measurement results of the modulator dynamic range is over 84 dB. Measured peak SNDR = 77.51 dB, SNR = 80.08 dB are achieved for the bandwidth of BW = 94 kHz while a sinusoid differential \(-1\) dBFS input is sampled at 12 MS/s. The total analog power consumption of the modulator is 0.37 mW while the supply voltage is 1.1 V.     

Comparative analysis of CMOS circuits of a thermometer-to-binary encoder for integrated flash analog-to-digital converters

The speed of a flash analog-to-digital converter (ADC) is limited by both the comparator response time in the input analog part of the circuit and the delay time of the encoder that converts the thermometer code on the comparator outputs into the output straight binary code. In this paper, we consider the problems of the synthesis of CMOS circuits of encoders for integrated flash ADCs. New encoder circuit designs with a reduced delay are proposed. The comparative analysis of the main characteristics of CMOS circuits of encoders based on the data of circuit simulation for the 180 nm MOSFET technology is presented.     

A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm² in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW     

Low-Voltage Analog Tripler Circuit

A new low-voltage CMOS tripler is presented in this paper. It is realized by the square-law characteristics of MOS transistors operating in saturation. The proposed circuit has been fabricated in a 0.8 m CMOS process. Experimental results have been given to demonstrate the feasibility of the proposed circuit. It is expected to be useful in low-voltage analog signal-processing applications.     

Low-Power CMOS Interface for Recording and Processing Very Low Amplitude Signals

In this paper, we describe a low-power low-voltage CMOS very low signal acquisition analog front-end of sensor electronic interfaces. These interfaces are mainly dedicated to biomedical implantable devices. In this work, we focus on the implantable bladder controller. Since the nerve signal has very low amplitude and low frequency, it is, at first fed to a low-voltage chopper amplifier to reduce the flicker (1/f) noise and then amplified with a programmable gain high CMRR instrumentation amplifier. This is followed by an analog signal processing circuit to rectify and bin-integrate (RBI) the amplified signal. The resulting RBI is then converted to digital and transferred to the implant's central processor where information about bladder can be extracted. The numerous analog modules of the system have been implemented in CMOS 0.35 μm, 3.3 V technology. The design, simulation and measurement results of the proposed interface are presented. At supply voltage of 2.2 V the power dissipation is less than 1.4 mW, the input equivalent noise is 56 nV/ $\sqrt {{\text{Hz}}} $ and the error in RBI calculation is less than 0.15%.