An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

Microwave frequency interconnection line model of a wafer level package

In this paper, we introduce the microwave transmission characteristics of interconnection lines on a wafer level package (WLP) and also propose a precise microwave-frequency model of the WLP interconnections. The slow wave factor (SWF) and attenuation constant are measured and discussed. High-frequency measurement is described, based on two-port S-parameter measurements, using an on-wafer microwave probe with a frequency range of up to 5 GHz. The extracted model is represented in the form of distributed lumped circuit model elements and can be easily merged into SPICE simulations. From the extracted model, it was found that line capacitance and inductance per unit length are 0.110 pF/mm and 0.286 nH/mm, respectively. We have successfully applied the extracted model to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, it was found that the WLP has better high-frequency performance, because of its low package inductance, compared with the /spl mu/BGA package, but longer propagation delay, because of the relatively high package capacitance.     

Modeling and sensitivity analysis of circuit parameters for flip-chip interconnects using neural networks

This paper presents a neural network-based technique for modeling and analyzing the electrical performance of flip-chip transitions. A lumped element model using a simple pi equivalent circuit is used to characterize the electrical properties of the flip-chip bond. Statistical experimental design is used to extract the electrical parameters for flip-chip characterization from measurements and full-wave simulations up to 35 GHz. The extracted data is used to train back-propagation neural networks to obtain an accurate model of the pi equivalent circuit components and s-parameters as a function of layout parameters. The prediction error of the models is less than 5%. The models are used to obtain response surfaces for the entire range of variation of layout parameters. The neural network models are subsequently used to perform sensitivity analysis. All electrical parameters are shown to be sensitive to conductor overlap. The inductance and capacitance of the pi equivalent circuit are sensitive to the bump height. However, the return loss (S₁₁) is insensitive to the change in bump height. The coplanar waveguide width has a significant impact on the s-parameters, as it affects the matching of flip-chip transitions     

High-frequency on-chip inductance model

The effect of random signal lines on the on-chip inductance is quantitatively investigated, using an S-parameter-based methodology and a full wave solver, leading to an empirical model for high-frequency inductance. The results clearly indicate that the random signal lines as well as designated ground lines provide return paths for gigahertz-frequency signals. In particular, quasi TEM-wave-like propagation mode is observed above 10 GHz, revealing a unique relationship between capacitance and inductance of the signal line. Incorporating the random capacitive coupling effect, our frequency-dependent RLC model is confirmed to be valid up to 100 GHz.     

Electrical characterization of ball grid array packages fromS-parameter measurements below 500 MHz

Ball grid array (BGA) packages have been characterized from one port S-parameter measurements by shorting and opening the connection on the ball side of BGA packages. Transmission line parameters (resistance, inductance and capacitance) using the Γ equivalent circuit model are extracted from the measured S₁₁ parameter. Extracted resistances are strongly dependent on frequency, but extracted inductances and capacitances are nearly constant up to 500 MHz. Extracted capacitances are well matched to those measured from an LCR meter and calculated from a three-dimensional (3-D) simulator, Capacitance in a transmission line plays an important role in electrical performance for packages so that we may model a transmission line as a single capacitor. Extracted capacitances using the single capacitor model also well represent the measured S₁₁. These results suggest that the single capacitor model can be efficiently used for the transmission line model in BGA packages up to 500 MHz     

A unified RLC model for high-speed on-chip interconnects

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model.     

Microwave frequency crosstalk model of redistribution line patterns on wafer level package

As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer S-parameter measurements and was fitted to the measurements made at up to 5 GHz.     

A Multiscale Description of the Electronic Transport within the Hierarchical Architecture of a Composite Electrode for Lithium Batteries

The broadband dielectric spectroscopy technique is applied, for the first time, to a composite material used as an electrode for lithium battery. The electrical properties (permittivity and conductivity) are measured from low (a few Hz) to microwave (a few GHz) frequencies. The results demonstrate that the broadband dielectric spectroscopy technique is very sensitive to the different scales of the electrode architecture involved in electronic transport, from interatomic distances to macroscopic sizes, as well as to the morphology at these scales, coarse or fine distribution of the constituents. This work opens up new prospects for a more fundamental understanding and more rational optimization of the electronic transport in composite electrodes for lithium batteries and other electrochemical energy storage technologies (including other batteries, supercapacitors, low‐ and medium‐temperature fuel cells), electrochemical sensors and conductor–insulator composite materials.     

A fast 3D modeling approach to electrical parameters extraction ofbonding wires for RF circuits

Bonding wires are extensively used in integrated circuit (IC) packaging and circuit design in RF applications. An approach to fast three-dimensional (3D) modeling of the geometry for bonding wires in RF circuits and packages is demonstrated. The geometry can readily be used to extract electrical parameters such as inductance and capacitance. An equivalent circuit is presented to model the frequency response of bonding wires. To verify simulation accuracy, test structures have been made and measured. Excellent agreement between simulated and measured data is achieved for frequencies up to 10 GHz. The model is well suited for the design and analysis of circuits for cellular phone communication (i.e., order 2 GHz) and future wireless communication (i.e., order 5 GHz)     

SOI全介质隔离与高频互补双极兼容工艺

ＳＯＩ材料的全介质隔离技术与高频互补双极工艺的结合是研制抗辐照能力强、频带宽、速度高的集成运算放大器的理想途径，从实验的角度提出了一种ＳＯＩ材料全介质隔离与高频互补双极工艺兼容的工艺途径。     

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).     

Modeling and Layout Optimization of Differential Inductors for Silicon-Based RFIC Applications

A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.     

Accurate measurement of ground-ring inductance in ball grid arraypackage

A new technique has been developed to measure the ground-ring inductance in a ball grid array (BGA) package. A simple parallel LC circuit is used to model the ground-ring parasitics at frequencies up to 1 GHz. After connecting an SMA connector to the ground ring of the BGA package, a network analyser can be used to measure the reflection coefficient (S₁₁) up to 1 GHz from which the ground-ring inductance can be extracted. It has been found that the ground-ring inductance depends very strongly on the phase of S₁₁. This leads to the advantage of excellent accuracy for the extracted quantities. The experimental ground-ring inductance data for a variety of BGA packages are verified by Ansoft simulation results     

High-isolation CPW MEMS shunt switches. 1. Modeling

This paper, the first of two parts, presents an electromagnetic model for membrane microelectromechanical systems (MEMS) shunt switches for microwave/millimeter-wave applications. The up-state capacitance can be accurately modeled using three-dimensional static solvers, and full-wave solvers are used to predict the current distribution and inductance of the switch. The loss in the up-state position is equivalent to the coplanar waveguide line loss and is 0.01-0.02 dB at 10-30 GHz for a 2-μm-thick Au MEMS shunt switch. It is seen that the capacitance, inductance, and series resistance can be accurately extracted from DC-40 GHz S-parameter measurements. It is also shown that dramatic increase in the down-state isolation (20⁺ dB) can be achieved with the choice of the correct LC series resonant frequency of the switch. In part 2 of this paper, the equivalent capacitor-inductor-resistor model is used in the design of tuned high isolation switches at 10 and 30 GHz     

Unified AC model for the resonant tunneling diode

A physics-based model is shown to yield the small-signal equivalent circuit of the resonant tunneling diode (RTD) including an analytic expression for both the quantum inductance and capacitance. This model unifies previous models by Brown et al. for quantum inductance and by Lake and Yang for quantum capacitance, and extends the RTD SPICE model of Broekaert. The equivalent circuit has been fit to both current-voltage and microwave S-parameter measurements of AlAs-InGaAs-InAs-InGaAs-AlAs RTDs from 45 MHz to 30 GHz and over biases from 0 to 0.81 V. Good agreement between the model and measurement is shown.     

Measurement and Characterization of Microwave Interaction between Integrated Distributed Feedback Laser Diode and Electro-Absorption Modulator

Integrated electro-absorption-modulated distributed feedback laser diodes (EMLs) are attracting much interest in optical communications for the advantages of a compact structure, low power consumption, and high-speed modulation. In integrated EML, the microwave interaction between the distributed feedback laser diode (DFB-LD) and the electro-absorption modulator (EAM) has a nonnegligible influence on the modulation performance, especially at the high-frequency region. In this paper, integrated EML was investigated as a three-port network with two electrical inputs and a single optical output, where the scattering matrix of the integrated device was theoretically deduced and experimentally measured. Based on the theoretical model and the measured data, the microwave equivalent circuit model of the integrated device was established, from which the microwave interaction between DFB-LD and EAM was successfully extracted. The results reveal that the microwave interaction within integrated EML contains both the electrical isolation and optical coupling. The electrical isolation is bidirectional while the optical coupling is directional, which aggravates the microwave interaction in the direction from DFB-LD to EAM.     

Experimental analysis of transmission line parameters in high-speedGaAs digital circuit interconnects

Transmission line properties of typical high-speed interconnects were experimentally investigated by fabricating and characterizing coplanar strips on semi-insulating GaAs substrates. The strips have thicknesses of about 2500 Å or 5000 Å and widths of 4, 6, or 8 μm so as to be representative of on-chip interconnects in high-speed GaAs digital circuits. Measurements are carried out up to 18 GHz, and the pertinent line parameters, such as resistance, capacitance per unit length, and characteristic impedance, are extracted using the measured S-parameters. The measurement results confirm the quasi-TEM properties of such interconnects. In all cases, the measured distributed capacitance and inductance are sensitive to frequency whereas the resistance is found to increase as much as 38% for the widest and thickest conductors     

A comparison of quantum-mechanical capacitance-voltage simulators

We have systematically compared the results of an extensive ensemble of the most advanced available quantum-mechanical capacitance-voltage (C-V) simulation and analysis packages for a range of metal-oxide-semiconductor device parameters. While all have similar trends accounting for polysilicon depletion and quantum-mechanical confinement, quantitatively, there is a difference of up to 20% in the calculated accumulation capacitance for devices with ultrathin gate dielectrics. This discrepancy leads to large inaccuracies in the values of dielectric thickness extracted from capacitance measurements and illustrates the importance of consistency during C-V analysis and the need to fully report how such analysis is done     

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.     

Accurate RF electrical characterization of CSPs using MCM-D thin film technology

The thin film multilayer multichip module-deposited (MCM-D) technology of IMEC is used for characterising the RF electrical performance of two types of chip scale packages (CSPs). The measurement technique called MCM-on-package-on-MCM (MoPoM) enables accurate measurements and de-embedding in the gigahertz (GHz) range of frequencies. Wafer processing of the MCM-D technology allows for several design structures to be integrated on a single mask. The packages chosen are a 120-pin plastic ball grid array (PBGA) and an 80-pin polymer stud grid array (PSGA). Lumped element models extracted from measurements and three-dimensional simulations show good agreement with the measurements up to 6 GHz for the BGA and the PSGA. The electrical performance of the packages is compared at 1.8 GHz (GSM), 2.4 GHz (Bluetooth), and 5.2 GHz (HiperLAN) and at 5.2 GHz both the packages exhibit a return loss of lower than -10 dB and hence cannot be used in most cases without design improvement. We also show that the influence of encapsulant is significant while transmission line detuning due to the package is not significant at microwave frequencies. We also briefly mention about the crosstalk effects. We demonstrate the significant degradation in the performance of a 5.2 GHz MCM-D low noise amplifier (LNA) after packaging. A significant improvement in package performance is observed by conjugate matching the package interconnects.