一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环

用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μm CMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).     

A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology

The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than -72 dBc while consuming 88 mW from a 1.45-V supply.     

Low-jitter PLL based on symmetric phase-frequency detector technique

A low-jitter phase-locked loop (PLL) with a symmetric phase frequency detector has been proposed. The phase-frequency detector is composed of only two symmetric XOR gates. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45 degrees. The PLL was fabricated in a 0.18 μm CMOS technology. Measured phase noise of the PLL output at 500 kHz offset from the 5 GHz center frequency is −102.6 dBc/Hz. The circuit exhibits a low rms jitter of 2.06 ps and a capture range of 280 MHz. The power dissipation excluding the output buffers is only 21.6 mW from a 1.8 V supply.     

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende...     

A 1.6-GHz CMOS PLL with on-chip loop filter

A 1.6-GHz phase locked loop (PLL) has been fabricated in a 0.6-μm CMOS technology. The PLL consists of an LC-tank circuit, divider, phase detector with charge pump, and an on-chip passive loop filter. When the oscillator is open loop, it exhibits -115 dBc/Hz phase noise at a 600-kHz offset from the carrier. The PLL occupies an active area of 1.6 mm² and dissipates 90 mW from a single 3-V supply     

基于电感电容振荡器的电荷泵锁相环的设计

设计并实现了一种采用电感电容振荡器的电荷泵锁相环,分析了锁相环中鉴频/鉴相器(PFD)、电荷泵(CP)、环路滤波器(LP)、电感电容压控振荡器(VCO)的电路结构和设计考虑。锁相环芯片采用0.13μm MS&RF CMOS工艺制造。测试结果表明,锁相环锁定的频率为5.6～6.9 GHz。在6.25 GHz时,参考杂散为-51.57 dBc;1 MHz频偏处相位噪声为-98.35 dBc/Hz;10 MHz频偏处相位噪声为-120.3 dBc/Hz;在1.2 V/3.3 V电源电压下,锁相环的功耗为51.6 mW。芯片总面积为1.334 mm2。     

带有自适应频率校准单元的26~41 GHz锁相环

采用45 nm SOI CMOS工艺,设计了一种带有自适应频率校准单元的26~41 GHz 锁相环。该锁相环包括输入缓冲器、鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、高速时钟选通器、分频器和频率数字校准单元。采用了基于双LC-VCO的整数分频锁相环,使用了自适应频率选择的数字校准算法,使得锁相环能在不同参考时钟下自适应地调整工作频率范围。仿真结果表明,该锁相环的输出频率能够连续覆盖26~41 GHz。输出频率为26 GHz时,相位噪声为-103 dBc/Hz@10 MHz,功耗为34.64 mW。输出频率为41 GHz时,相位噪声为-96 dBc/Hz@10 MHz,功耗为35.44 mW。     

Design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1–1500 MHz

This paper is concerned with the design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1–1500 MHz. The focus is on the circuit configuration and performance parameters of the basic analog units of the PLL: the stabilized bias unit, phase-frequency detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The data examined are obtained by measurements on ICs fabricated by a 0.25-or 0.18-μm established CMOS technology. The circuit configurations are presented of VCOs that are tunable up to 1–1.3 GHz or up to over 2 GHz; they are designed to be implemented in a 0.25-or 0.18-μm technology, respectively. Also addressed is the design of the digital section of PLL synthesizers with a tuning range extending from 1 to over 1000 MHz. The PLL frequency and step responses, current consumption, and jitter performance are presented and investigated.     

A 30-MHz hybrid analog/digital clock recovery circuit in 2-μmCMOS

A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 95% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 p.p.m./°C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW, and the active area is 30000 mil² in a 2-μm single-poly double-metal n-well CMOS process     

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

利用TSMC的O．18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明：在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4．7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112．3 dBe/Hz。芯片面积仅为0．6mm×O．6 mm,采用1.8 V电源供电,功耗低于90 mW。     

低抖动的480 MHz CMOS电荷泵式锁相环

本文设计了一款用于USB2.0时钟发生作用的低抖动、低功耗电荷泵式锁相环电路。其电路结构包含鉴频/鉴相器、电荷泵、环路滤波器、压控振荡器和分频器。电路设计是基于CSM0.18μmCMOS工艺,经HSPICE仿真表明,锁相环输出480MHz时钟的峰峰值抖动仅为5.01ps,功耗仅为8.3mW。     

一种具有相位噪声跟踪补偿的全数字锁相环频率合成器

为了实现频率合成器中的相位噪声跟踪补偿和降低全数字锁相环的复杂性,本文提出了一种新的基于全数字锁相环的频率合成器。它采用了一种低复杂度的数字鉴频鉴相器和非线性相位/频率判决电路以及数控振荡器,从而显著降低了硬件复杂性。同时结构中采用的非线性相位和频率判决电路能够很好地实现噪声跟踪和快速的相位/频率捕获,数控振荡器能够获得高的频率分辨率(大约6kHz)和大的线性频率调谐范围。通过采用90nm CMOS工艺制造的ADPLL实验结果表明,本文所提出的基于全数字锁相环的频率合成器能够实现从100kHz到6MHz的可控环路带宽和相当好的带内相位噪声跟踪性能。     

A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12/spl les/N/spl les/17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-/spl mu/m CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6dBc/Hz at 1-MHz offset and spurs of -52 dBc.     

创新单级环形振荡器的研制

提出了一款创新的单级环形振荡电路.该电路通过采用交叉耦合结构,制造额外的极点,使单级放大电路的相位交点总是发生在增益交点之前,此时根据巴克豪森准则,电路在环路相移为180°时增益仍然大于1,因此电路可持续振荡.此外,为了验证该振荡器的实用性,设计了一款以该振荡器作为VCO的可编程锁相环.电路采用标准0.5 μm CMOS工艺制造,流片结果显示该电路最高能工作在1.005 GHz,此时相位噪声达到-81 dBc/Hz@1 MHz.     

Cell-based fully integrated CMOS frequency synthesizers

A family of standard cells for phase-locked loop (PLL) applications is presented. The applications are processed using a 1.5 μm, n-well, double-polysilicon, double-layer metal CMOS process. Applications include frequency synthesis for computer clock generation, disk drives, and pixel clock generators for computer monitors, with maximum frequencies up to 80 MHz. The synthesizers require no external components since the loop filter and oscillator are on chip with the phase frequency detector and the charge pump. Special voltage and current reference cells are discussed. Analysis of noise sources in the PLL demonstrates the need for reducing the phase noise of the system. A low phase noise is achieved through supply rejection techniques and by placing the oscillator in a high-gain feedback loop to minimize its noise contributions. Laboratory measurements of completed silicon show synthesizers with exceptionally linear gain, as well as transient responses and phase noise similar to predicted results     

A digitally controlled PLL for SoC applications

A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-/spl mu/m standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.     

电流模式CMOS高频集成锁相环

本文报道了一种电流模式高频ＣＭＯＳ锁相环,该锁相环由鉴相器、低通滤波器及电流控制高频振荡器组成。采用２μｍ工艺参数,用ＰＳＰＩＣＥ（ＬＥＶＥＬⅡ）进行模拟表明,该电路能在１７ＭＨｚ￣５０ＭＨｚ的频率范围内工作。     

Fully integrated standard cell digital PLL

A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm²     

A low-jitter 125-1250-MHz process-independent and ripple-poleless0.18-μm CMOS PLL based on a sample-reset loop filter

This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18-μm CMOS process. A sample-reset loop filter architecture is used that averages the oscillator proportional control current which provides the feedforward zero over an entire update period and hence leads to a ripple-free control signal. The ripple-free control current eliminates the need for an additional filtering pole, leading to a nearly 90° phase margin which minimizes input jitter peaking and transient locking overshoot. The PLL damping factor is made insensitive to process variations by making it dependent only upon a bandgap voltage and ratios of circuit elements. This ensures tracking between the natural frequency and the stabilizing zero. The PLL has a frequency range of 125-1250 MHz, frequency resolution better than 500 kHz, and rms jitter less than 0.9% of the oscillator period