Interdigitated Microstrip Coupler Design

A design procedure for four-line interdigitated couplers is presented which provides excellent agreement between performance and actual coupler dimensions. The inclusion of a correction term for the finite metal thickness of the microstriplines is significant. Using existing odd-and-even mode impedance data of only two coupled lines in the array actual coupling coefficients in the 2.5-6.5-dB range are predictable to within /spl plusmn/0.05 dB. Graphs are shown which relate fabrication tolerances of dielectric constant and physicaf fine dimensions to deviations in coupling and characteristic coupler impedance. The design was verified on 3-, 5-, and 6-dB couplers in the 1-5-GHz frequency range.     

Multilayer MMIC directional couplers using thin dielectric layers

Low-loss and small-sized MMIC directional couplers utilizing a multilayer structure composed of coupled thin-film transmission lines on a GaAs wafer surface are newly proposed. The fundamental characteristics of the couplers are discussed through calculations by numerical analysis, and the performance of the couplers and an application to reverse-phase hybrid ring are demonstrated. The results show that a 3 dB coupler can be designed within a 0.8 mm×0.8 mm area for a center frequency of 20 GHz. Coupling losses of 3.7 dB±0.2 dB over a 4-GHz bandwidth and isolation of better than 26 dB in the frequency range of 0-30 GHz are achieved. The proposed coupler configurations can be applied to the high-density and multifunction integration of MMIC's     

Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p/sup -/silicon substrates

A 900-MHz single-pole double-throw (SPDT) switch with an insertion loss of 0.5 dB and a 2.4-GHz SPDT switch with an insertion loss of 0.8 dB were implemented using 3.3-V 0.35-/spl mu/m NMOS transistors in a 0.18-/spl mu/m bulk CMOS process utilizing 20-/spl Omega//spl middot/cm p/sup -/ substrates. Impedance transformation was used to reduce the source and load impedances seen by the switch to increase the power handling capability. SPDT switches with 30-/spl Omega/ impedance transformation networks exhibit 0.97-dB insertion loss and 24.3-dBm output P/sub 1dB/ when tuned for 900-MHz operation, and 1.10-dB insertion loss and 20.6-dBm output P/sub 1dB/ when tuned for 2.4-GHz operation. The 2.4-GHz switch is the first bulk CMOS switch which can be used for 802.11b wireless local area network applications.     

Simdified 12-GHz Low-Noise Converter with Mounted Planar Circuit in Waveguide (Short Papers)

A 12-GHz low-noise converter consisting of a planar circuit mounted in waveguide is described. This circuit consists of a metal sheet with proper patterns that is inserted in the middle of a waveguide parallel to the E plane. All circuit elements required for the converter are pressed or etched. This circuit is very useful for low-cost mass production and good performance. A measured noise figure of 4.5 dB was obtained with a 12-GHz signal frequency and a 420-MHz intermediate frequency.     

Frequency-reconfigurable two-port antenna for mobile phone operating over multiple service bands

A frequency-reconfigurable antenna for a mobile phone with small volume is proposed. The proposed antenna consists of a planar inverted F-antenna (PIFA) with volume of 4times36times5timesmm³ and a monopole antenna embedded in the same space. The two antennas are excited by two separate feeds with a common ground plane. A switch is used in the PIFA for frequency-reconfigurable operation. The PIFA can cover either LTE (698-806-MHz) or GSM900 (880-960-MHz) depending on the state of the switch. The monopole antenna can cover either PCS1900 (1.85-1.99-GHz) and m-WiMAX (3.4-3.8-GHz) or WLAN 802.11a (5.15-5.35-GHz) depending on the state of the switch. The antenna gain is in the range of -1.99-0.61-dBi over 700-MHz-2-GHz bands and 2.39-4.62-dBi over the bands higher than 3-GHz. The proposed antenna is shown to have good radiation characteristics.     

Backward directional coupler for weak coupling of double-sided microstrip lines using longitudinal double-slots

A backward directional coupler for double-sided microstrip lines is presented. Aligned microstrip lines are coupled via two parallel slots in the common ground plane. This design works well for weak coupling smaller than 20 dB and has some advantages over the single-slot coupler. Geometrical dimensions of the proposed coupler design are presented for coupling values of 20, 25 and 30 dB, together with measurements for a 30 dB coupler.     

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digitalwireless communication

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC consisting of receive, transmit, and local oscillator (LO) sections is presented. The transmit section achieves an unwanted sideband suppression of -43 dBc, LO leakage of -59 dBc, and third-order spurious rejection of -70 dBc. The transmit output noise level is -165 dBc/Hz at a 20-MHz offset from the carrier. The on-chip very high-frequency oscillator has a phase-noise level of -106 dBc/Hz at 100-kHz offset when operating at 800 MHz. The receive section has 36 dB of gain with 36 dB of gain range in 12-dB steps. The transceiver IC has been fabricated using a 25-GHz f_t silicon bipolar process and is designed to operate over a supply-voltage range of 2.7-5.0 V     

5-GHz Low Power Current-Reused Balanced CMOS Differential Armstrong VCOs

This letter proposes 5-GHz low power differential Armstrong voltage controlled oscillators (VCOs) based on balanced topology. One designed VCO uses two single-ended Armstrong VCOs coupled to each other in parallel by balanced structure. The other current-reused VCO uses two single-ended Armstrong VCOs stacked in series. The former VCO oscillates from 4.96 to 5.34GHz and the power consumption is 3.9mW at 0.6-V supply voltage. The latter operates from 4.98 to 5.45GHz and dissipates 2.59mW at 1.8-V supply voltage. The measured phase noises are about -116.71dBc/Hz and -110.02dBc/Hz at 1-MHz offset frequency from 5.1-GHz band, respectively. The former and the latter VCO have an advantage of low power consumption and provide a good figure of merit of about -185dBc/Hz and -180dBc/Hz, respectively     

A wide-band GaAs monolithic spiral quadrature hybrid and itscircuit applications

The design, performance, and circuit applications of a 2-6-GHz GaAs monolithic spiral quadrature coupler are presented. This 90° coupler uses lumped spiral inductors and metal-insulator-metal (MIM) capacitors and is very small in size (14 mil×26 mil). The measured relative phase difference between the coupled and direct port over the 3:1 bandwidth was 93°±6°. Applications of this broadband hybrid in reflection phase-shifter, image-reject downconverter, and I-Q downconverter circuits have also been successfully demonstrated based on this structure     

Top-Wall and Branch-Waveguide Hybrids for Millimeter Wavelengths (Correspondence)

Top-wall and multiple-branch waveguide couplers were developed as hybrid junctions for millimeter wavelengths, and their electrical characteristics were measured. For construction of the 55-GHz top-wall coupler, electroforming techniques were used; for the 94-GHz branch-guide coupler, the branch lines were cut directly into the wall of the main guide. Copper losses were less than 0.2 dB for the two types of couplers.     

An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with<10-Hz RF carrier resolution

A 2.5-GHz/900-MHz dual fractional-N/integer-N frequency synthesizer is implemented in 0.35-μm 25-GHz BiCMOS. A ΔΣ fractional-N synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip ΔΣ modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling are considered. The fractional-N synthesizer offers less than 10-Hz frequency resolution having the in-band noise contribution of -88 dBc/Hz for 2.47-GHz output frequency and -98 dBc/Hz for 1.15-GHz output frequency, both measured at 20-kHz offset frequency. The prototype dual synthesizer consumes 18 mW with 2.6-V supply     

一种宽带高方向性微带定向耦合器

文中设计了一种小型化的具有高方向性的多节微带线定向耦合器。通过将耦合微带线分段处理,得到由一节1/4波长段和两节1/8波长段组合的多段耦合器。非均匀介质微带耦合线中奇偶模相速度的差异导致微带定向耦合器的方向性较差。文中通过在耦合器馈线拐角处采用1/4圆弧提高了方向性。通过优化仿真设计实现了10 GHz耦合器,耦合度为25 dB,并且从6~14 GHz的方向性优于30 dB。与传统的并联耦合线耦合器相比,文中所提出的耦合器具有更小尺寸和更加出色的方向性,且实测和模拟仿真基本一致。     

A 8-GHz SiGe HBT VCO Design on a Low Resistive Silicon Substrate Using GSML

A practical layout method called ground shield microstrip lines (GSML) is investigated for the reliable design of high frequency interconnection lines on a low resistive silicon substrate. GSML facilitates the prediction of parasitic networks at the expense of introducing negligible loss. The microwave performance of a GSML line structure is compared to that of a conventional metal line on the same standard silicon substrate (20 Omegamiddotcm). Then, the GSML structure is applied to an 8-GHz SiGe heterojunction bipolar transistor (HBT) voltage-controlled oscillator (VCO) circuit. The GSML method replaces the post layout simulation and reduces iteration time, increasing design efficiency. A fully integrated differential tuning SiGe HBT 8-GHz VCO is designed and tested. The measured phase noise for the VCO is dBc/Hz at 1-MHz offset with an output power of dBm.     

A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers

A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in an RF Si-bipolar process with an f/sub T/ of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP/sub 3/ (+15.5-dBm OIP/sub 3/) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA DC current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with -10 to -41-dB S/sub 11/ is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 /spl times/ 0.9 mm/sup 2/. The circuit is suitable for area-efficient multiband multistandard low-IF receivers.     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

On the conception and analysis of a 12-GHz push-push phase-locked DRO

This paper describes the design and behavior of a 12-GHz push-push dielectric resonator oscillator in a phase-locked environment. This phase-locked dielectric resonator oscillator (PLDRO) differs from conventional designs on many fronts. First, it uses a push-push oscillator for its improved phase noise and reduced fundamental frequency. Second, the phase detection is implemented at a 3-GHz IF as an alternative to detecting at RF using a sampling phase detector (PD). Finally, the push-push PLDRO is tuned via coupled microstrip lines to minimize oscillator loading. These modifications are intended to minimize the risk of PLDRO lock failures by maintaining a constant PD gain via amplifiers operating at P/sub 1dB/, and by halving the DRO fundamental frequency using the push-push approach. Experimental results indicate a fundamental suppression of 27 dBc, and single-sideband phase noise densities of -105, -110, and -125 dBc/Hz at 10-kHz, 100-kHz, and 1-MHz offsets, respectively, from a 12-GHz carrier.     

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

A 10-bit 20-MHz A/D converter for high-quality video systems such as high-definition television, video tape recorders for business use, and digital video cameras is described. This LSI circuit uses a standard two-step parallel architecture, includes automatic gain adjustment and digital two-bit error correction, and has a sample-and-hold circuit on the chip. It is fabricated by a 4.5-GHz f_T. 3-μm-rule standard bipolar technology. Its die size is 25 mm² , and its power consumption is 900 mW, which is about half of the lowest values reported to date. The converter can digitize video signals of up to 8.5 MHz at a conversion frequency of 20 MHz. The error in differential gain is 0.5 percent, and the error in differential phase is 0.5°     

Low-loss compact Butler matrix for a microstrip antenna

This paper presents the design and realization of a double four-port Butler matrix to feed a four-column array antenna with two orthogonally polarized signals (to obtain polarization diversity). The main goals of this study are the reduction of the size and the losses of the network. In order to meet those requirements, a bi-layer structure, the suspended stripline, has been adopted to support the circuit. Moreover, the complete network has been integrated in a single unit. The double four-port Butler matrix has been etched on both sides of the suspended substrate to solve the problem of the cross between the lines. The broadside suspended 3-dB directional coupler has been chosen for the design of the 3-dB hybrid coupler. In order to change the side of the suspended substrate, contactless transitions have been used. The network is designed to work within the range of frequencies of the GSM-900-MHz standard: band 880 MHz-960 MHz, center frequency f₀=920 MHz. Measured losses for a 4×4 Butler matrix are 0.3 dB     

A Wideband Bandpass Filter With Wide Upper Stopband Using Stepped-Impedance Cascadable 180 ° Hybrid Rings

This letter proposes a wideband bandpass filter by cascading two 3-dB stepped-impedance cascadable 180deg hybrid rings with a pair of stepped-impedance lines. Thanks to the stepped-impedance lines, a broad upper stopband is achieved. The stepped-impedance vertically installed planar (VIP) coupler is used to implement the ideal 180deg phase inverter and crossovers. The experimental results show that this 2-GHz center frequency, fourth order filter has a 10-dB return loss bandwidth of 92.5% and upper stopband rejection levels of better than -20 dB up to 6.8 GHz. This proposed filter achieves wide passband and broad stopband performance simultaneously.     

Microstrip line directional couplers with high directivity

Novel uniplanar backward directional couplers are analysed and designed. Microstrip parallel coupled lines and asymmetrical delay lines enable a multi-sectioned coupler to enhance directivity as well as the coupling. Single and multi-sectioned couplers at 1.8 GHz have been designed and measured, providing excellent directivity.