Turbo判决反馈均衡(DFE)技术分析及改进

由于无线信道的多径衰落引起的符号间干扰(ISI)极大地影响了接收端的信号质量,为了对抗ISI引起的信号畸变,通常要在接收端进行信道均衡。该文分析了基于MMSE-DFE的Turbo均衡原理并提出两种低复杂度的改进算法。仿真结果表明,这两种算法性能良好。     

基于线性化因子更新的频域迭代判决反馈均衡

迭代块判决反馈均衡(Iterative Block Decision Feedback Equalization,IBDFE)是单载波频域均衡中一种行之有效的非线性均衡算法,但算法计算复杂度随迭代次数增加而增大。本文针对传统IBDFE算法的不足提出一种基于线性因子更新的频域迭代判决反馈均衡算法,利用了线性因子更新来降低均衡器复杂度,并引入修正因子计算反馈滤波器系数以避免性能损失。仿真结果表明,所提出算法性能与传统IBDFE算法相比复杂度降低且在误比特率为10-5时有0.12 dB的性能增益,与已有的低复杂度算法(Low-Complexity IBDFE,LC-IBDFE)相比有0.1 dB的性能增益。      

一种改进的单载波块迭代判决反馈均衡算法

针对低复杂度的块迭代频域判决反馈均衡算法在迭代过程中对判决误差概率设置不够合理的缺陷,提出一种改进的块迭代频域判决反馈均衡算法,该算法通过在迭代过程中合理的设置判决误差概率,从而提高系统的性能。与低复杂度的块迭代频域判决反馈均衡算法相比,该算法能够获得更好的性能,并且具有较低的复杂度。     

并行级联LDPC码译码迭代终止准则研究

提出了两种低复杂度的终止准则,以用于降低PCGC（并行级联Gallager码,parallel concatenated gallagercode）的译码器运算量.这两种准则通过观察边信息方差的改变情况,来判断是否终止译码器迭代.计算机仿真结果证明,这些终止准则可有效地降低译码器运算量,且不影响译码器误比特率性能.     

并行级联Gallager码的动态最大外迭代次数译码方案的研究

PCGC(Parallel Concatenated Gallager Code,并行级联Gallager码)是将LDPC(Low Density Parity Check,低密度奇偶校验)码运用于并行级联编码形式而得到的一种新型编码,它的译码器采用双层迭代的形式.传统的PCGC译码器采用FMSIN(Fixed Maximum Super Iteration Number,固定最大外迭代次数)的方案,在信道SNR(Signal-to-Noise Ratio,信噪比)较低时会导致译码器平均迭代次数,也即译码器复杂度偏高.针对于此,本文提出一种根据信道信噪比状况动态调整译码器中最大外迭代次数的方案,并通过计算机仿真,验证了运用此方案后,译码器复杂度可得到较大程度的降低.     

改进的SC-FDE块迭代判决反馈均衡器

在单载波频域传输(SC-FDE)系统中,块迭代判决反馈均衡器(IBDFE)明显提升了传统线性频域均衡器的性能.未知发送信号与迭代判决信号的相关因子估计是其关键技术,直接影响均衡器的性能.首先对IBDFE相关因子估计算法进行了改进,同时提出一种基于独特字(UW)帧结构的估计方法.该方法利用独特字的已知性和恒包络性进行判决,基于此判决方式使相关因子得到更精准的估计.实验结果表明,两种方法对IBDFE的性能有较为明显的提升.     

稀疏多径信道中单载波频域均衡系统的联合干扰抵消和均衡

针对大时延稀疏多径信道条件下的单载波频域均衡系统(SC-FDE),本文提出了一种新的迭代均衡结构,记为IC-FDE-DFE。IC-FDE-DFE可以缩短频域均衡所需的循环前缀(CP)的长度,提高稀疏多径信道下SC-FDE系统的带宽效率和功率效率。与单纯的时频域混合判决反馈均衡器(H-DFE)相比,IC-FDE-DFE能够充分利用信道的‘稀疏’特性,其中的均衡器具有较低的运算复杂度和设计复杂度。仿真结果表明,IC-FDE-DFE能够在迭代过程中逐渐抵消大时延多径的影响,逼近H-DFE的理想性能。     

单载波频域均衡系统中一种简化的IBDFE算法

在单载波频域均衡系统中,线性均衡算法虽然简单易行,但是其抑制噪声干扰和符号间干扰的能力有限,因此需要引入非线性的反馈和迭代机制以进一步提升系统性能.迭代块判决反馈均衡（Iterative Block Decision Feedback Equalization,IBDFE）就是一种行之有效的非线性算法,但其缺点是计算复杂度高.鉴于此,在IBDFE结构的基础上,利用最小均方误差准则,推导出了一种新的简化算法.之后,对简化后算法和现有低复杂度算法的均方误差（Mean Square Error,MSE）性能进行了理论分析和比较,并在两种无线多径衰落信道下对三种不同的算法进行了仿真.结果表明,在所给信道条件下,这种算法在迭代两次后已基本收敛.同时,仿真也验证了MSE分析的结论.最后,对算法复杂度的分析和比较表明,提出的简化算法相比传统IBDFE算法,其误比特率性能有所下降,但能有效地减小计算量.     

一种改进的SC-FDE块迭代判决反馈均衡器

单载波频域均衡(SC-FDE)系统能有效地对抗频域选择性衰落信道。块迭代判决反馈均衡(IBDFE)是单载波频域均衡系统中一种有效的非线性均衡算法,但是其计算复杂度较高,且复杂度与迭代次数成正比。鉴于此,提出一种改进算法,在改进算法中,将接收信号经过MMSE均衡得到发送信号估计值作为传统算法反馈支路输出,前馈支路结构保持不变。对比传统IBDFE算法,迭代被取消,故降低了计算复杂度。对传统IBDFE算法和改进IBDFE算法性能进行比较,实验结果证明:改进IBDFE算法性能在与传统IBDFE算法性能相似的条件下降低了计算复杂度。     

基于块迭代的判决反馈均衡算法研究

为了对抗短波信道深衰落和线性频域均衡存在的剩余码间串扰(Inter-Symbol Interference,-ISI)影响,研究基于块迭代的判决反馈均衡(Block Iterative Decision Feedback Equalization,IB-DFE)算法,对不同参数情况下的判决反馈均衡算法性能进行了对比分析...     

基于并行均衡框架的Turbo均衡

为了解决在Turbo均衡中由迭代引起的均衡延迟问题,两种分别对应于最大后验概率(MAP)和线性最小均方误差(LMMSE)均衡算法的并行均衡方案被提出。通过理论分析、仿真验证以及最后的硬件实现复杂度的分析研究表明,对于上述两种并行均衡方案,可以保证在小的硬件实现复杂度开销以及几乎没有性能损失的前提下,大大降低其均衡延迟。     

并行级联分组码的一种新的迭代译码算法

并行级联分组码比串行级联分组码具有更高的码率,基于LLR计算的Turbo迭代译码算法使其内外分量码均做到了软判决译码。通过引入校正因子a（m）,将接收信息与子译码器的输出软信息进行线性叠加反馈能在省去繁琐的LLR计算的情况下实现并行级联分组码的Turbo迭代译码。仿真研究表明,若将译码器的输出进行简单的相关运算,可进一步改善译码器性能。     

The Effect of Block Interleaving in an LDPC‐Turbo Concatenated Code

The effect of block interleaving in a low density parity check (LDPC)‐turbo concatenated code is investigated in this letter. Soft decoding can be used in an LDPC code unlike the conventional Reed‐Solomon (RS) code. Thus, an LDPC‐turbo concatenated code can show better performance than the conventional RS‐turbo concatenated code. Furthermore, the performance of an LDPC‐turbo code can be improved by using a block interleaver between the LDPC and turbo code. The average number of iterations in LDPC decoding can also be reduced by a block interleaver.     

Turbo码的一种并行译码方案及相应的并行结构交织器研究

Turbo码基于MAP算法译码的递推计算所引入高的译码延迟限制了Turbo码在高速率数据传输中的应用。为了解决这个问题,该文提供了一种降低译码延迟的并行译码方法。并行处理方案的实现必须通过适当的交织以避免两个译码器对外信息读写的数据冲突。该文在分析了任意无冲突交织方式可能性的存在之后,给出了设计任意地适用于并行处理方案的S随机交织器的方法。仿真验证了并行译码方案的误比特性能。     

分布式MIMO的Turbo检测算法

当信道码为卷积码时,针对V-BLAST类空时码的分布式MIMO,该文提出了两种迭代检测算法：最大似然迭代接收机及一种低复杂度的迭代检测接收机。最大似然迭代检测接收机的复杂度为O(2MTSlogM),低复杂度的迭代检测接收机的复杂度为 O(M2TM2RS2M) 。在准静态、单径瑞利衰落信道中,对低复杂度的迭代检测接收机的误码率性能进行了计算机仿真验证,与非迭代的迫零检测相比,低复杂度的迭代检测接收机节约比特信噪比约7.5dB;在相同的误码率下,迭代6次与迭代1次相比,可节约3dB的比特信噪比;随着迭代次数的增加,迭代效果越来越小。     

A Parallel Concatenated Convolutional-Based Distributed Coded Cooperation Scheme for Relay Channels

In this paper, we investigate a coded cooperation diversity scheme suitable for L-relay channels operating in the soft-decode-and-forward (soft-DF) mode. The proposed scheme is based on parallel concatenated convolutional codes (PCCC). To improve the overall performance through diversity, the coded cooperation operates by sending the systematic and the first parity outputs via L?+?1 independent fading paths. Instead of using only a centralized turbo code system at the source node, we have proposed a DCC scheme, where the first recursive systematic coding is done at both source and relay nodes. At the destination, the received replicas are combined using the maximal ratio combining (MRC). The entire codeword, comprising the MRC sequence and the second parity part, is decoded via the maximum a-posteriori (MAP) algorithm and turbo decoding principle. We analyze the proposed scheme in terms of bit error rate (BER). In fact, we define the explicit upper bounds for error rate assuming Binary phase shift keying (BPSK) transmission for fully interleaved channels with channel state information (CSI). We use the Rayleigh fading channels with independent fading. Our study shows that the full diversity order is achieved when the source-relay link is more reliable than the other links. Otherwise, the diversity decreases. However, in both cases, it is shown that significant performance improvements are possible to achieve over non-cooperative coded systems. Theorical and simulation results are presented to demonstrate the efficacy of the proposed scheme.     

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.      

A Turbo Detection and Sphere-Packing-Modulation-Aided Space-Time Coding Scheme

A recently proposed space-time block-coding (STBC) signal-construction method that combines orthogonal design with sphere packing (SP), referred to here as STBC-SP, has shown useful performance improvements over Alamouti's conventional orthogonal design. In this contribution, we demonstrate that the performance of STBC-SP systems can be further improved by concatenating SP-aided modulation with channel coding and performing demapping as well as channel decoding iteratively. We also investigate the convergence behavior of this concatenated scheme with the aid of extrinsic-information-transfer charts. The proposed turbo-detected STBC-SP scheme exhibits a "turbo-cliff" at E_b/N₀=2.5 dB and provides E_b/N₀ gains of approximately 20.2 and 2.0 dB at a bit error rate of 10 ^-5 over an equivalent-throughput uncoded STBC-SP scheme and a turbo-detected quadrature phase shift keying (QPSK) modulated STBC scheme, respectively, when communicating over a correlated Rayleigh fading channel.A condensed version of this paper was presented at VTC'04 Fall, LA, USA     

非二进制Turbo级联码的性能分析

该文在分析了非二进制Turbo码的译码算法的基础上,提出了非二进制Turbo码和具有良好纠突发错误的RS码级联的非二进制Turbo级联码系统模型。该系统采用缩短的RS码(204, 188)作为外码,非二进制Turbo码作为内码的串行级联方式,内码和外码之间用深度为12的交织器隔开,译码时, 非二进制Turbo码分别采用Symbol-by-Symbol Log-MAP和SOVA算法。仿真结果显示,与二进制Turbo级联码系统相比,该系统具有误码率低,延时时间短,频带利用率高等优点。