Design of random doping fluctuation resistant structures of semiconductor devices

An automated technique is presented for the computation of the doping profiles that minimize the intrinsic fluctuations of various parameters induced by random doping fluctuations in semiconductor devices. The technique is based on the computation of the doping sensitivity functions of the parameters under consideration and the constrained minimization of the standard deviation of fluctuations by using the Lagrange multipliers technique. The technique is then applied to the minimization of the random doping induced fluctuations of the threshold voltage in 40-nm channel length MOSFET device.     

Sensitivity of single- and double-gate MOS architectures to residual discrete dopant distribution in the channel

The effect of a single discrete impurity in the channel of Fully-Depleted Single- and Double-Gate MOSFETs is analyzed by means of 3D Monte Carlo simulation. The Double-Gate (DG) architecture appears to be less sensitive to the dopant perturbation than the Single-Gate (SG) counterpart. For an N-channel device the influence of a P-type impurity on the current-voltage characteristics is shown to be strongly dependent on the impurity position in the channel. The maximum current degradation is obtained for an impurity located about 5 nm from the source-end of the channel. The I _on reduction reaches 6% in DG and 10.5% in SG. A small current enhancement (less than 2%) is induced by an N-type impurity. These results are analyzed in terms of velocity profile between source and drain.     

Transport in silicon nanowires: role of radial dopant profile

We consider the electronic transport properties of phosphorus (P) doped silicon nanowires (SiNWs). By combining ab initio density functional theory (DFT) calculations with a recursive Green’s function method, we calculate the conductance distribution of up to 200 nm long SiNWs with different distributions of P dopant impurities. We find that the radial distribution of the dopants influences the conductance properties significantly: surface doped wires have longer mean-free paths and smaller sample-to-sample fluctuations in the cross-over from ballistic to diffusive transport. These findings can be quantitatively predicted in terms of the scattering properties of the single dopant atoms, implying that relatively simple calculations are sufficient in practical device modeling.     

Design and fabrication of a differential capacitive three-axis SOI accelerometer using vertical comb electrodes

A differential capacitive three-axis silicon-on-insulator (SOI) accelerometer using vertical comb electrodes fabricated by using surface-micromachining technique has been developed. The accelerometer structures consist of only the device layer of a SOI wafer without lower or upper electrodes. The vertical comb electrodes of this device have structures different from conventional vertical comb electrodes. The bottom faces of both movable and fixed electrodes are in the same plane at their initial positions but their heights are different. Three-axis acceleration can be sensed with differential capacitance detection by using only these vertical comb electrodes. The device structures were successfully fabricated using self-alignment and Deep-RIE processes. As an initial result, the capacitance changes against three-axis acceleration were observed and the device sensitivities to three-axis accelerations were measured. The capacitance sensitivities of X, Y and Z-axis were 1.01, 0.898 and 0.989 fF/G, respectively. Copyright © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Subthreshold Mobility Extraction for SOI-MESFETs

Mobility calculation is a difficult task due to the stochastic nature of the particles in a device. This is especially true for a device operated in the sub-threshold region because the transport is a combination of diffusion and drift albeit diffusion dominated. As a result, one can calculate the mobility based on the drift and the diffusion techniques for a device operated in the subthreshold regime. We have developed a transport model, based on the solution of the Boltzmann Transport Equation, for modeling n-channel silicon-on-insulator (SOI) MOSFETs and MESFETs using the Ensemble Monte Carlo technique. All relevant scattering mechanisms for the silicon material system have been included in the model. The model is used to calculate both the diffusion coefficient and the drift based mobility and the results are compared with available experimental values. The mobility of the equivalent SOI MESFET device is a factor of 3–5 times higher than that of the MOSFET in the sub-threshold regime.     

Enhancing the design and performance of a gate-all-around (GAA) charge plasma nanowire field-effect transistor with the help of the negative-capacitance technique

A gate-all-around charge plasma nanowire field-effect transistor (GAA CP NW FET) device using the negative-capacitance technique is introduced, termed the GAA CP NW negative-capacitance (NC) FET. In the face of bottleneck issues in nanoscale devices such as rising power dissipation, new techniques must be introduced into FET structures to overcome their major limitations. Negative capacitance is an efficient effect that can be incorporated into a device to enhance its performance for low-power applications and help to reduce the operating voltage. The Landau–Khalatnikov equation can be applied in such cases to obtain the effective bias. To determine the effects of negative capacitance, lead zirconate titanate (PZT) ferroelectric material, a ceramic material with perovskite properties, is adopted as a gate insulator. This approach diminishes the supply voltage and reduces the power dissipation in the device. Excluding their polarization properties, ferroelectric materials are similar to dielectric materials, and PZT offers abundant polarization with improved reliability and a higher dielectric capacitance. Without proper tuning of the thickness of the PZT material, hysteresis behavior mat occur. Hence, the thickness of the PZT material (t_FE) is an essential parameter to optimize the device performance and achieve a reduced threshold voltage for the GAA CP NW NC-FET device proposed herein. Furthermore, varying the thickness of the PZT ferroelectric material can also enhance the performance. When using the highest values of t_FE, improved outcomes with an analogously lower operating voltage are observed. The effects of varying t_FE on the performance characteristics of the device including the drain current, transconductance, polarized charge, etc. are also interpreted herein.

     

Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator

The intrinsic parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. The interface charge in the recess regions of high electron mobility transistors (HEMTs) has a considerable effect on the overall device performance. We have employed a 3D parallel drift-diffusion device simulator to study the impact of interface charge fluctuations on the I-V characteristics of nanometre HEMTs. For this purpose, two devices have been analysed, a 120 nm gate length pseudomorphic HEMT with an In_0.2Ga_0.8As channel and a 50 nm gate length InP HEMT with an In_0.7Ga_0.3As channel.     

Modified octree mesh generation for Manhattan type structures with narrow layers applied to semiconductor devices

One of the most important steps in the process of semiconductor device simulation, or any other numerical simulation based on finite elements, finite differences or similar standard techniques, is the discretization of the domain of the problem. A mesh must be generated, and its properties determine the stability of the numerical solver, computational time and quality of the solution. In this paper an octree‐based mesh generator is presented. The classical model for octree generation have been modified to optimize the programme for special regions of interest in the semiconductor device problem, Manhattan structures with very narrow layers. Using this technique, several meshing patterns have been tested and compared. Numerical results of the generation of general meshes are presented to demonstrate the efficiency of the algorithms from two points of view: mesh quality and computational effort. It has been successfully applied to the modelling and simulation of different transistors, High Electron Mobilty Transistors (HEMTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Copyright © 2006 John Wiley & Sons, Ltd.     

A novel approach to extract accurate design parameters of PiN diode

Accurate modelling of PiN diode transient behaviour is necessary to extract design parameters which are not documented in datasheets. To meet this requirement, this paper introduces a novel approach giving the possibility to identify accurate parameters of a given device. The used technique is based only on two stages. First, the design parameters are initialized and optimized. Second, they are refined by minimizing the cost function which depends on the transient switching parameters (I_RM, V_RM and t_rr). With a simple and CPU time-saving approach this technique leads to extract design parameters without necessarily knowing the exact technological architecture of the PiN diode. Moreover, in order to validate the proposed approach and the parameter extraction procedure three commercial diodes are tested. A good agreement between experimental and simulation data is obtained. Copyright © 2007 John Wiley & Sons, Ltd.     

DC analysis and design of a PWM buck converter operated as a dynamic power supply

Modern energy transmission and signal reproduction techniques rely upon power amplifiers that must operate with high efficiency. An increasingly popular technique for addressing this problem involves replacing the fixed power amplifier supply voltage V _{D D} with a controlled, variable voltage provided by a dynamic power supply. Although pulse‐width modulated dc‐dc buck converters typically function as fixed‐output supplies, this paper provides new theoretical dc analysis for operation wherein the output voltage is controlled and continuously variable over a wide range. A design procedure for the variable‐output buck converter is derived. Key device parameters affecting converter speed and efficiency are identified. The dc analysis and design procedure are verified experimentally, with calculated and measured parameters shown to be in good agreement. Copyright © 2016 John Wiley & Sons, Ltd.     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

A tabular source approach to modelling and simulating device and circuit noise in the time domain

Simulation of device and circuit noise at low frequencies is often carried out as part of a small‐signal ac analysis. Moreover, circuit simulators with rf analysis capabilities usually specify circuit performance in terms of S parameters and model high‐frequency noise in terms of noise waves and correlation matrices. It is also unusual to find circuit simulators that extend noise simulation to the time domain. This is particularly true for software packages developed from SPICE 2g6 or 3f5. This paper introduces a simple tabular noise source technique, which adds time‐domain noise to semiconductor device models and integrated circuit macromodels. The proposed technique is suitable for use with any general purpose circuit simulator. To demonstrate the power of the suggested approach the text describes time‐domain noise extensions to the SPICE diode, BJT, JFET, MOSFET and MESFET models. These noise extensions have been implemented and tested with the ‘Quite universal circuit simulator’ (Qucs). Copyright © 2011 John Wiley & Sons, Ltd.     

A new adaptive multi‐bias S‐parameter measurement algorithm for transistor characterization

A new adaptive measurement algorithm is described for the control of an automated S‐parameter measurement set‐up used to characterize transistors for non‐linear modelling. The procedure differs from previous algorithms in that is uses both the device DC‐ and S‐parameter data to identify DC bias regions where the device characteristics are changing rapidly. By placing more bias points in these areas and less data points in regions where the device response stays constant, the non‐linear behaviour of the device can be characterized more accurately while keeping the total volume of the experimental data and hence the measurement time to an acceptable level. Experimental results are presented that illustrates the operation of the adaptive algorithm as well as the influence that the selection procedure has on non‐linear modelling results. Copyright © 2005 John Wiley & Sons, Ltd.     

Planar analysis of radial-line power dividers

The resonant mode field expansion technique presented in previous papers to analyse one- or two-port microstrip structures of different geometrical shapes is now applied to multiport radial lines. In particular, a radial-line n-way power divider is considered. This device allows, under certain hypotheses, an equiphase and equiamplitude splitting of an input signal. The Z matrix formulation has been derived and utilized to obtain the scattering parameters for the circuit. The numerical results are in good agreement with both experimental and theoretical data presented in the literature. The low number of resonant modes required to obtain satisfactory numerical convergence allows a substantial reduction of the computing time with respect to other more complicated approaches.     

Noise immune dielectric modulated dual trench transparent gate engineered MOSFET as a label free biosensor: proposal and investigation

We propose and investigate a biosensor based on a transparent dielectric-modulated dual-trench gate-engineered metal–oxide–semiconductor field-effect transistor (DM DT GE-MOSFET) for label-free detection of biomolecules with enhanced sensitivity and efficiency. Various sensing parameters such as the I_ON/I_OFF ratio and the threshold voltage shift are evaluated as metrics to validate the proposed sensing device. Additionally, S_Vth (the V_th sensitivity) is also analyzed, considering both positively and negatively charged biomolecules. In addition, radiofrequency (RF) sensing parameters such as the transconductance gain and the cutoff frequency are taken into account to provide further insight into the sensitivity of the proposed device. Furthermore, the linearity, distortion, and noise immunity of the device are evaluated to confirm the overall performance of the biosensor at high (GHz) frequency. The results indicate that the proposed biosensor exhibits a S_Vth value of 0.68 for positively charged biomolecules at a very low drain bias of 0.2 V. The proposed device can thus be used as an alternative to conventional FET-based biosensors.

     

Lumped-element filtering power dividers

A power divider is ideally a lossless reciprocal device performing vector summation of two or more input signals, which is an extremely important circuit component in wireless communication systems or radar systems. In this paper, a general concept of lumped-element power divider is discussed. Then, a semi-analytical synthesis technique is presented. General odd-mode and even-mode analysis method is proposed for multi-port symmetrical network and applied in the analysis of N-way lumped-element power dividers. The transmission networks and the matching networks can be synthesized step by step, which greatly simplify their analysis. The transmission networks can be synthesized by those well-known synthesis techniques for two-port networks, and thus the transmission property of power dividers can be accurately controlled. The matching networks are determined by optimization to ensure certain isolation between the output ports. The design procedure is simple and accurate. Apart from the capability of power division, power dividers are also able to play the role of impedance transform and signal processing. Some examples of power dividers with filtering capability are presented for demonstration. In this paper, a general concept of lumped-element power divider is discussed. Then, a semi-analytical synthesis technique is presented. General odd-mode and even-mode analysis method is proposed for multi-port symmetrical network and applied in the analysis of N-way lumped-element power dividers. Transmission networks and matching networks can be synthesized step by step, which greatly simplify their analysis. Apart from the capability of power division, power dividers are also able to play the role of impedance transform and signal processing.     

Optimization of linear systems for 3D parallel simulation of semiconductor devices: Application to statistical studies

The 3D simulators are nowadays essential in semiconductor device modelling in order to study fluctuation effects when devices are scaled to gate lengths approaching nanometre dimensions. To take into account these effects it is necessary to perform statistical studies, which have a high computational cost. The resolution of the linear systems generated by the discretization of partial differential equations is the most time‐consuming part of the simulation process. In this paper we propose an optimization of the linear system solution procedure based on domain decomposition methods implemented in a 3D parallel drift–diffusion device simulator. We have also carried out an analysis of the parallel performance of the device simulator. Numerical results show superlinear efficiency values up to 62 processors in the solution of the Poisson equation. The results were obtained on a Cluster HP Integrity Superdome. Copyright © 2008 John Wiley & Sons, Ltd.     

Comprehensive comparison of FACTS devices for exclusive loadability enhancement

A complete comparison of a number of well‐known flexible alternating current transmission system (FACTS) devices for static voltage stability enhancement is presented. Various performance measures including power–voltage (P–V) curves, voltage profiles, and power losses are compared under normal and contingency conditions. The importance of proper modeling of FACTS devices, including the DC side, is emphasized because, at their limits, most of these devices behave like a fixed capacitor or inductor. A simple placement technique of series FACTS devices and unified power flow controller (UPFC) is proposed considering exclusive loading margin enhancement. A new idea of loading margin increase per cost is proposed to find the appropriate FACTS devices for investment. The paper provides a guide for utilities to have an appropriate choice of FACTS device for enhancing static voltage stability and loading margin by comparing technical merits and demerits of each of these devices in terms of system performance. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Efficient three‐dimensional parallel simulations of PHEMTs

An efficient 3D semiconductor device simulator is presented for a memory distributed multiprocessor environment using the drift–diffusion (D–D) approach for carrier transport. The current continuity equation and the Poisson equation, required to be solved iteratively in the D–D approach, are discretized using a finite element method (FEM) on an unstructured tetrahedral mesh. Parallel algorithms are employed to speed up the solution. The simulator has been applied to study a pseudomorphic high electron mobility transistor (PHEMT). We have carried out a careful calibration against experimental I–V characteristics of the 120 nm PHEMT achieving an excellent agreement. A simplification of the device buffer, which effectively reduces the mesh size, is investigated in order to speed up the simulations. The 3D device FEM simulator has achieved almost a linear parallel scalability for up to eight processors. Copyright © 2005 John Wiley & Sons, Ltd.     

Towards the global modeling of InGaAs-based pseudomorphic HEMTs

We utilize a 3D full-band Cellular Monte Car- lo (CMC) device simulator to model ultrashort gate length pseudomorphic high-electron-mobility transistors (p-HEMTs). We present the static dc device characteristics and rf response for gate lengths ranging from 10 nm to 50 nm. Preliminary passive results using 3D full-wave Maxwell solver are also presented to illustrate the usefulness of and insight that a future coupled full-band/full-wave simulator will provide in more accurately, modeling the high frequency performance of p-HEMTs.