A new approach to simulating n-MOSFET gate current degradation byincluding hot-electron induced oxide damage

A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N_it ) and oxide trapped charge (Q_ox) were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N_it and Q_ox has thus been proposed. Furthermore, the individual contributions of N_it and Q_ox to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I_G,max. Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and flash EEPROM devices     

A new method for characterizing the spatial distributions ofinterface states and oxide-trapped charges in LDD n-MOSFETs

Previous studies showed that simultaneous determination of the interface states (Nit) and oxide-trapped charges (Q_ox) in the vicinity of the drain side in MOS devices was rather difficult. A new technique which allows a consistent characterization of the spatial distributions of both hot-carrier-induced Nit and Q_ox is presented. Submicron LDD n-MOS devices were tested and charge pumping measurements were performed. The spatial distributions of both Nit and Q _ox have been justified by two-dimensional (2-D) device simulation of the I-V characteristics for devices before and after the stress. Comparison of the drain current characteristics between simulation and experiment shows very good agreement. Moreover, results show that fixed-oxide charge effect is less pronounced to the device degradation for the experimental LDD-type n-MOS devices     

A new charge-pumping technique for profiling the interface-statesand oxide-trapped charges in MOSFETs

A new charge-pumping method has been developed to characterize the hot-carrier induced local damage. By holding the rising and falling slopes of the gate pulse constant and then varying the high-level (V_GH) and base-level (V_GL) voltages, the lateral distribution of interface-states (N_it(x)) and oxide-trapped charges (Q_ox(x)) can be profiled. The experimental results show that during extracting Q_ox(x) after hot-carrier stress, a contradictory result occurs between the extraction methods by varing the high-level (V_GH) and base-level (V_GL) voltages. As a result, some modifications are made to eliminate the perturbation induced by the generated interface-states after hot-carrier stress for extracting Q_ox(x)     

A unified approach to profiling the lateral distributions of bothoxide charge and interface states in n-MOSFET's under various biasstress conditions

A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N _it) and oxide charge (Q_ox) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N_it and Q_ox in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N_it and Q_ox under various bias stress conditions, such as the hot-electron stress (I_G,max), I_B,max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N_it and Q_ox has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, E²PROM cells since the above stress conditions, such as the I_G,max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively     

A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N_it) and oxide trap charges (Q_ox) under both channel-hot electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N_it and Q_ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes     

A new observation of band-to-band tunneling induced hot-carrierstress using charge-pumping technique [MOSFETs]

The lateral distributions of interface-states (N_it) and oxide-trapped charges (Q_ox) generated by band-to-band tunneling (BTBT) induced hot-carrier stress are analyzed by the new charge-pumping method. It is shown that the interface-states and oxide-trapped charges should originate from different types of carriers due to the separation of the locations of their peak values. The further evidence of the measured distribution of the interface-states in the band-gap shows that the carriers travelling toward the gate edge would be the dominant carrier for the generation of interface-states while the carriers travelling away from the gate edge will generate oxide-trapped charges through the help of the vertical electric field. These results should be very useful for the reliability analysis of flash memories     

A semi-empirical model for the field-effect mobility ofhydrogenated polycrystalline-silicon MOSFETs

The quantitative relationship between field-effect mobility (μ _FE) and grain-boundary trap-state density (N_t ) in hydrogenated polycrystalline-silicon (poly-Si) MOSFETs is investigated. The focus is on the field-effect mobility in MOSFETs with N_t 1×10² cm^-2. It is found that reducing N_t to as low as 5×10¹¹ cm^-2 has a great impact on μ_FE. MOSFETs with the N_t of 4.2×10¹¹ cm^-2 show an electron mobility of 185 cm²/V-s, despite a mean grain size of 0.5 μm. The three principal factors that determine μ_FE, namely, the low-field mobility, the mobility degradation factor, and the trap-state density N_t are clarified     

Features and mechanisms of the saturating hot-carrier degradationin LDD NMOSFETs

Propagation of defects from the sub-spacer region to the gate-overlapped LDD region in NMOSFETs is modeled using measurements and 2-D device simulation. It is argued that the saturation of degradation is caused by the saturating nature of this degradation length, as opposed to decreasing lateral electric field maxima (E_m) or increasing barrier height (φ_it) to defect creation. Two stage hot-carrier degradation was observed in our LDD NMOSFETs. The early mode (1000-3000 s) of the degradation is characterized by a sharp rate of degradation of the linear transconductance (g_m), and a reduction in the substrate current (I_B). In order to locate and quantify defects produced in this early mode degradation phase, we use the results of a combination of the floating gate technique and simultaneous measurements of the reverse (source and drain interchanged) saturation g_m's. These results help us build a 2-D simulation framework involving trapped negative charges in the oxide in the drain-side gate-edge region, partly under the gate and partly in the spacer region. We then use 2-D simulation and other measurements such as linear and saturation current degradation, I_B degradation, and charge pumping to confirm the location of the defects and help estimate their quantity. Simulation results also help us build an analytical model for defect propagation from the early mode to the late mode. The analytical model is seen to explain many features of the saturating nature of hot-carrier degradation     

Charge trap generation in LPCVD oxides under high field stressing

The degradation of low pressure chemical vapor deposited (LPCVD) oxides, prepared using silane and tetra ethyl ortho silicate (TEOS) as the source, has been investigated under high field stressing. The LPCVD oxides exhibit enhanced conductivity for the Fowler-Nordheim tunneling current, which is modeled as an effective lowering of potential barrier at the injecting electrode. The charge to breakdown (Q_bd) of LPCVD oxides depends on both the deposition chemistry and post deposition annealing condition. The change in interface-state density (ΔD_it), flatband voltage (ΔV_fb), and gate voltage (Δ|V_g|) during constant current stressing are studied to identify the degradation mechanism. We see a very good correlation between Q_bd and Δ|V_g|, indicating that the degradation in LPCVD oxides is dominated by bulk trap generation and subsequent charge trapping. We present a detailed theoretical analysis to substantiate this     

Performance evaluation of COFDM for digital audio broadcasting. II.Effects of HPA nonlinearities

For pt. I see ibid. vol.43, no.1, p.64-75, 1997. The effects of the high power amplifier (HPA) nonlinearities on the performance of the Eureka 147 DAB system are studied by computer simulation. The performance is determined for three types of HPA: a travelling wave tube amplifier (TWTA), a solid state power amplifier (SSPA) and a perfectly linearized amplifier (PLA). Two related performance criteria are used: (a) the degradation, resulting from HPA nonlinearities, in the E_b /N₀ ratio required at the receiver to maintain a bit error rate of 10^-4 and (b) the total power degradation. These degradations are measured as a function of the HPA output backoff (OBO). The effect, on the E_b/N₀ degradation, of linearizing only the phase or only the amplitude transfer characteristic of the TWTA and the SSPA is also assessed. Correcting the phase distortion alone in both HPAs is found to reduce the E_b/N₀ degradation by less than 0.5 dB. Linearization of the amplitude characteristic alone, on the other hand, can reduce the E_b/N₀ degradation by several dBs at small OBO values (<2 dB). The optimum output backoff which minimizes the total power degradation is between 2 and 3 dB for both the TWTA and the SSPA in a terrestrial mobile channel and between 1 and 2 dB in an AWGN channel. The optimum output backoff for the PLA is 2 dB in the terrestrial channel and between 1 and 2 dB in the AWGN channel. At the optimal operation point, the power saved by linearizing the amplitude and phase characteristics of the TWTA or the SSPA is about 0.6 dB for the terrestrial mobile channel and 0.4 dB for the AWGN channel     

Physical model of drain conductance, gd, degradation ofNMOSFET's due to interface state generation by hot carrierinjection

Degradation of analog device parameters such as drain conductance, g_d, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g_d degradation can be calculated from linear region transconductance, g_m, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g_d degradation calculated from g_m degradation fit well to the measured values of g_d degradation The dependence of the g_d degradation lifetime on L_eff has been also studied, this model also provides an explanation of the dependence on L_eff. The model is then useful for lifetime predictions of analog circuits in which g_d degradation is usually more important than g_m degradation     

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C_gb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I_dsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g_m) degradation and, eventually, cutoff frequency (f_T) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f_T is largely affected by local stress change, i.e., g_m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f_T is dominated by increased parasitic capacitance (C_gb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f_T has been observed through layout optimization for C_gb reduction by increasing the transistor active-to-SC spacing.     

The impacts of control gate voltage on the cycling endurance ofsplit gate flash memory

In this paper, the “erase” degradation in program/erase (P/E) cycling endurance of split-gate flash memory has been investigated. It is found that increasing the control-gate (CG) voltage (V_CG) during erasing can slow down the “window closure” of cycling endurance since a higher V_CG can “push” the FG potential into gradual part of I_Read-out -V_FG curve and in turn reduce the read-out current degradation. Moreover, the experimental results show that scaling down the gate oxide thickness under FG can effectively reduce the I_Read-out degradation in the cycling endurance test     

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_x, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I_on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th), relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_x, as the gate dielectric had ca. 1.73 times the mobility (mu_FE) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_x, TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, mu_FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO_x, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.     

Dynamic-stress-induced enhanced degradation of 1/f noise inn-MOSFETs

AC-stress-induced degradation of 1/f noise is investigated for n-MOSFETs with thermal oxide or nitrided oxide as gate dielectric, and the physical mechanisms involved are analyzed. It is found that the degradation of 1/f noise under AC stress is far more serious than that under DC stress. For an ac stress of V_G=0~0.5 V_D, generations of both interface states (ΔD_it) and neutral electron traps (ΔN_et) are responsible for the increase of 1/f noise, with the former being dominant. For another AC stress of V _G=0~V_D. a large increase of 1/f noise is observed for the thermal-oxide device, and is attributed to enhanced ΔN_et and generation of another specie of electron traps, plus a small amount of ΔD_it. Moreover, under the two types of AC stress conditions, much smaller degradation of 1/f noise is observed for the nitrided device due to considerably improved oxide/Si interface and near-interface oxide qualities associated with interfacial nitrogen incorporation     

Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

Hot carrier induced bipolar transistor degradation due to basedopant compensation by hydrogen: theory and experiment

New experimental and analytical results are presented which show that extrinsic and intrinsic base dopant compensation by hydrogen is responsible for large changes in the bipolar transistor parameters of emitter-base breakdown voltage (V_ebo), forward collector current (I_c) and series base resistance (R_bx) when such transistors are operated under avalanche and inverted mode stress conditions. A new physical model has been developed to explain the observed changes in V_ebo and I_c as a function of stress time, and the analytical results are shown to be well correlated with the experimental data. Lastly, the effects of degradation on transistor voltage gain bandwidth (f_max) and emitter coupled bipolar comparator delay (τ_delay) are assessed and discussed in terms of circuit performance degradation     

Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses

Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low V_d-stress and in high V_d-stress condition. Defect generation distribution along the channel appears to be different in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low V_d-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress     

A novel single-device DC method for extraction of the effectivemobility and source-drain resistances of fresh and hot-carrier degradeddrain-engineered MOSFET's

A new DC technique, the drain current-conductance method (DCCM), has been developed to extract the gate bias dependent effective channel mobility (μ_eff), and source and drain series resistance (R _s and R_d) of drain-engineered MOSFET's. The extraction of μ_eff, R_e, and R_d by DCCM is based on the DC measurements of drain current and conductance of a single device. The negligible difference between the measured and modeled (using the extracted parameters) linear drain current showed that the DCCM is accurate and effective for devices with different graded junction structures and channel lengths. Asymmetry between R_s and R_d for LDD p-MOSFET's was found to be more significant than for LATID n-MOSFET's. This asymmetry has invalidated many methods which utilized the assumptions of R_d=R_s for the extraction of device parameters. The DCCM was further applied to devices with nonuniform hot-carrier degradation. The μ_eff, R_s, and R_d of LATID n-MOSFET's degraded under different hot-carrier stress conditions were extracted. The increase in R_d is found to dominate the initial phase of hot-carrier degradation while the decrease in μ_eff intensifies as the stress duration increases. The extracted parameters have provided physical insight into the asymmetries of graded junctions and degradation mechanisms of hot-carrier stressed MOSFET's, The DCCM is especially useful for the extraction of SPICE parameters that are usable in circuit and reliability simulation     

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (V_g = V_d), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously ("concurrent HCI-NBTI"), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under V_g = V_d at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under V_g = V_d shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias.