基于集中式管理的缓存优化方案

针对分布式文件系统HDFS以流式的方式访问大文件时效率很高,但是为解决海量小文件的操作特别是频繁访问重复的小文件时效率比较低的问题,提出了一种基于集中式管理的缓存优化方案.该方案通过对缓存的小文件进行集中式管理,采用一种新的数据一致性管理机制,提高海量小文件的读取性能.实验结果表明,该方案有效地提高了小文件的读取效率,减少了小文件的访问时延.     

An efficient parallel-processing method for transposing largematrices in place

We have developed an efficient algorithm for transposing large matrices in place. The algorithm is efficient because data are accessed either sequentially in blocks or randomly within blocks small enough to fit in cache, and because the same indexing calculations are shared among identical procedures operating on independent subsets of the data. This inherent parallelism makes the method well suited for a multiprocessor computing environment. The algorithm is easy to implement because the same two procedures are applied to the data in various groupings to carry out the complete transpose operation. Using only a single processor, we have demonstrated nearly an order of magnitude increase in speed over the previously published algorithm by Gate and Twigg (1977) for transposing a large rectangular matrix in place. With multiple processors operating in parallel, the processing speed increases almost linearly with the number of processors. A simplified version of the algorithm for square matrices is presented as well as an extension for matrices large enough to require virtual memory.     

基于读写特征的分布式互斥算法

在LK算法基础上,提出一种对读写请求作不同互斥处理的分布式互斥算法——RWME(read/write mutual exclusion)算法.在同步延迟仍为T的前提下,降低了传统非令牌类型互斥算法的消息复杂度.在Lamport全局时戳的基础上,定义了适合于读写互斥的全局时戳——读写时戳,并由其来保证各读写进程互斥访问临界区的公平性和正确性.通过对算法的性能分析验证其是高效的,并给出了正确性证明.     

An on-chip march pattern generator for testing embedded memorycores

In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead     

An Efficient Pre-Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications

A large portion of silicon area and the energy consumed by the Viterbi decoder (VD) is dedicated to the survivor memory and the access operations associated with it. In this work, an efficient pre-traceback architecture for the survivor-path memory unit (SMU) of high constraint length VD targeting wireless communication applications is proposed. Compared to the conventional traceback approach which is based on three kinds of memory access operations: decision bits write, traceback read, and decode read, the proposed architecture exploits the inherent parallelism between the decision bit write and decode traceback operation by introducing pre-traceback operation. Consequently, the proposed pre-traceback approach reduces the survivor memory read operations by 50%. As a result of the reduction of the memory access operations, compared to the conventional 2-pointer traceback algorithm, the size of the survivor memory as well as the decoding latency is reduced by as much as 25%. Implementation results show that the pre-traceback architecture achieves up to 11.9% energy efficiency and 21.3% area saving compared to the conventional traceback architecture for typical wireless applications.     

基于DMA的大批量数据快速传输模块设计

针对Altera公司SOPC解决方案中,DMA模块无法直接读/写FPGA外设的情况,提出了基于Avalon总线流传输模式的通用DMA读/写控制模块的设计,设计了两个自定义外设,实现了DMA对FPGA外设的高速数据存取和Nios II与FPGA大批量数据的快速传输。介绍了Avalon-MM总线规范,阐述了系统架构以及DMA读控制器的设计,测试结果表明,该方法是一种高效可行的解决方案。     

RFID高频读写器防碰撞算法研究

基于对RFID(无线射频识别,Radio Frequency Identification)高频读写器防碰撞性能提高的目的,介绍了二进制搜索算法原理,并基于二进制搜索算法详尽研究了一种符合ISO/IEC 14443A规范的比特帧防碰撞算法,比特帧防碰撞算法能有效的实现高频读写器的防碰撞功能。此方法为解决RFID高频防碰撞问题,提高高频读写器性能具有重要的实用意义和指导意义。     

一种二维访问效率均衡的SAR数据矩阵转置方法

针对SAR成像矩阵转置效率偏低的问题,提出了矩阵分块三维映射法.该方法基于带有bank划分的存储介质并利用其数据访问特性,通过矩阵分块和跨bank优先数据访问方式将二维数据矩阵映射至存储介质的三维存储空间,能够充分发挥存储介质的数据访问效率.实测结果表明,该方法使二维数据的访问效率都接近于顺序访问的效率,极大提高了SAR成像的矩阵转置效率.     

基于JdbcTemplate的数据库访问处理

Spring JdbcTemplate简化了对数据库的访问处理,详细讨论了JdbcTemplate实现对数据库表格的增、删、改、查询的操作处理方法。分别针对多行数据结果集、单值结果的查询需求,给出相应的JdbcTemplate的不同方法调用。在数据更新处理中,讨论了完整SQL和带参数填充的SQL的方法调用形式。最后,结合文件内容的保存与恢复处理实例,介绍了大容量数据的读写,通过LobCreator对象的setBlobAsBinaryStream方法实现LOB数据的写入,通过LobHandler接口提供的系列方法可获取LOB数据。     

一种能耗优化的RAID小写预读方法

视频监控、备份、归档等应用产生海量存储数据，导致存储能耗急剧增加.S-RAID采用局部并行数据布局，可显著降低该类应用的存储能耗.为使更多磁盘待机节能，S-RAID通常执行"小写"操作，写操作时会额外引入等量的读操作，会显著降低性能.现有预读机制主要发生在文件级，无法感知RAID级小写引发的读旧数据、旧校验数据等读操作，因此不会也无法预读该类数据.为此，提出一种面向S-RAID的RAID级小写预读算法，由小写操作触发并在RAID级执行预读，根据S-RAID的数据布局方式，大粒度异步预读小写需要的旧数据、旧校验数据，有效减少I/O数和寻道数，提高磁盘的利用率.该方法可显著提高S-RAID的写性能，并且不依赖于任何额外硬件，具有更高的可用性.     

Multi-valued static random access memory (SRAM) cell with single-electron and MOSFET hybrid circuit

A new multi-valued static random access memory (MVSRAM) cell with a hybrid circuit consisting of a single-electron (SE) and MOSFETs is proposed. The previously reported MVSRAM with an SE-MOSFET hybrid circuit needs two data lines, one bit line for write operations and one sense line for read operations, to improve the speed of the read-out operation, but the proposed cell has only one data line for read/write operations, resulting in a memory area that is much smaller than that of the previous cell, without any reduction of read-out speed.     

A ferroelectric DRAM cell for high-density NVRAMs

The operation of a ferroelectric DRAM (dynamic random access memory) cell for nonvolatile RAM (NVRAM) applications is described. Because polarization reversal only occurs during nonvolatile store/recall operations and not during read/write operations, ferroelectric fatigue is not a serious endurance problem. For a 3-V power supply, the worst-case effective silicon dioxide thickness of the unoptimized lead zirconate titanate film studied is less than 17 Å. The resistivity and endurance properties of ferroelectric films can be optimized by modifying the composition of the film. This cell can be the basis of a very-high-density NVRAM with practically no read/write cycle limit and at least 10¹⁰ nonvolatile store/recall cycles     

A quasi-matrix ferroelectric memory for future silicon storage

We proposed a new quasi-matrix ferroelectric memory for use in future silicon-storage media. The memory unit consists of multiple ferroelectric capacitors and one access transistor. Each capacitor stores 1 bit of data, and the access transistor is shared by several capacitors. Compared with conventional crosspoint matrix type FeRAMs, which cause a signal degradation by read/write disturbance, this memory limits the disturbing frequency to an acceptable level by accessing the memory unit as a whole. Crosstalk noise was also minimized by applying a unique access scheme. This memory has a scalability by adopting built-in sense circuits, and enables an extremely high packing density with three-dimensional multistacking structures of memory cells.     

SAR实时成像高效矩阵转置研究和实现

矩阵转置是SAR成像处理中的重要运算,SAR成像的实时巨量数据处理对基于片外存储的矩阵转置算法效率提出了很高的要求,而目前的实时转置算法实现的效率都偏低.文中通过分析片外存储特性,研究和提出适用于SAR实时成像的矩阵转置算法,占有片内资源少,读写平衡且效率高,配置灵活可组合成较复杂的矩阵转置形式,目前已成功应用于多种模式的SAR成像处理.     

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body–source voltage dynamically. Proper usage of low-threshold voltage (L-\(V_{\mathrm{t}}\)) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power–delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.     

DACPCC:一种包含访问权限的云计算数据访问控制方案

目前云计算访问控制技术最常用的加密体系是CP-ABE,但传统的CP-ABE加密体系中没有涉及用户的访问权限问题,数据提供者只能让用户去读取数据而不能写数据,访问控制机制不灵活,且效率低.针对这一不足,本文提出了一种包含访问权限的高效云计算访问控制方案DACPCC,该方案在CP-ABE基础上设置了权限控制密钥来加密云中的数据,数据提供者通过对权限控制密钥的选择来控制数据的访问权限.文章对DACPCC进行了详细的设计,并做了安全性证明和实验验证,结果表明DACPCC能够让数据提供者对其数据资源进行权限控制,并且是安全和高效的.     

一种支持更新操作的数据空间访问控制方法

数据空间是一种新型的数据管理方式,能够以pay-as-you-go模式管理海量、动态、异构的数据。然而,由于数据空间环境下数据的动态演化、数据描述的细粒度和极松散性等原因,难于构建有效的访问控制机制。该文提出一个针对数据空间环境下极松散结构模型,重点支持更新操作的细粒度和动态的访问控制框架。首先定义更新操作集用于数据空间的数据更新,提出支持更新操作的映射方法,可将动态数据映射到关系数据库中;给出支持更新操作权限的数据空间访问控制规则的定义,并分析与关系数据库的访问控制规则二者转换的一致性;然后提出具有可靠性和完备性的访问请求动态重写算法,该算法根据用户的读/写访问请求检索相关访问控制规则,使用相关权限信息重写访问请求,从而实现支持动态更新的细粒度数据空间访问控制。理论和实验证明该框架是可行和有效的。     

Write Disturbance Modeling and Testing for MRAM

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C-test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-mum technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.     

Coded modulation and precoding for electron-trapping opticalmemories

This paper develops coding and signal processing approaches for a novel optical recording channel that arises from electron-trapping phosphor materials. The recording medium allows multiple reads and writes, and one important feature is that the read process serves to erase the disk. This feature would enable vendors of prerecorded video to provide customers with one-time services. For applications where this feature is not desirable, the data can be immediately rewritten. From a communications viewpoint, the most important feature of this new channel is that, subject to a peak constraint, it supports a continuum of recording levels. The combination of read and write processes creates a partial-response channel, and the ability to write a continuum of levels makes it possible to employ precoding techniques, such as the one developed by Tomlinson (1971) and by Miyakawa and Harashima (1969). This is fundamentally different from magnetic data storage, where the read/write process creates a partial-response channel but where it is only possible to write two levels at the input to that channel. This paper shows that the use of precoding and coset codes can significantly improve upon the recording densities (and recording rates) that can be achieved by using M-ary run length constrained codes to eliminate intersymbol interference (ISI) at the output of the read/write process. The approach presented is applicable to any optical recording channel that supports a continuum of recording levels     

A novel nonvolatile memory cell suitable for both flash andbyte-writable applications

The structure, operation, and fabrication of a novel EEPROM/flash cell and array architecture are described. The cell is about half the size of the traditional floating gate tunnel oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) cell when laid out with the same design rules. This approach has a simple fabrication sequence and requires minimum overhead circuitry rendering it especially suitable for embedded applications. Characterization shows this approach has good retention and has million cycle endurance. Both read and write disturbs are characterized. There are large margins for both types of disturbs. In fact, the data on write disturbs show the disturb margins to be so large that disturb margin can be safely traded off for reduced stress on select transistors