A Robust and Scalable Constant-$g_m$ Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without any special devices, such as floating-gate or depletion-mode transistors. Very small variations (less than ) have been achieved without sacrificing the large-signal behavior. The proposed circuit is proven effective for both long-channel and deep sub-micron CMOS technologies and is suitable for VLSI cell libraries, audio/video, embedded mixed-signal system-on-chip (SoC), and other applications. A prototype amplifier with rail-to-rail input common-mode range has been designed and fabricated in a standard 0.35-m CMOS technology. Experimental results confirm the effectiveness and robustness of proposed techniques.     

Three-dimensional CMOS SOI integrated circuit usinghigh-temperature metal-induced lateral crystallization

A three-dimensional (3-D) CMOS integrated circuit was fabricated based on the conventional CMOS SOI technology. The first layer of transistors was formed on the SOI. The second layer of transistors was built on large-grain polysilicon-on-insulator (LPSOI). The recrystallized film was formed by the recrystallization of amorphous silicon using metal-induced lateral crystallization (MILC). The devices from the lower and upper layers were characterized and the result indicated that the SOI and LPSOI devices have similar electrical characteristics. The 3-D circuit design and layout considerations are introduced. The 3-D CMOS inverters were demonstrated with p-channel devices stacking over the n-channel ones. The ring-oscillator showed that the 3-D circuit has 30% reduction in the layout area and it operated at power supply as low as 0.5 V. The lower propagation delay and load capacitance suggest that 3-D circuit has higher performance than the conventional two-dimensional (2-D) circuit     

Performance of CMOS differential circuits

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique     

Precise characterization of long-distance mismatch of CMOS devices

A new test structure is presented for the characterization of long-distance mismatch of complimentary metal-oxide-semiconductor (CMOS) devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for 0.5-, 0.35-, and 0.25-μm CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices. Examples for linear and nonlinear distance dependencies are shown. The long-distance mismatch has to be taken into account in circuit designs with short channel transistors and with narrow resistors     

Four-quadrant analog multiplier based on CMOS inverters

In the article a new implementation of four-quadrant analog multiplier in CMOS technology is proposed. The circuit is based exclusively on CMOS inverters (or similar two-transistor blocks) and operates using quarter square technique. The outstanding feature of the circuit is an extreme suitability for low voltage operation and full compatibility with digital CMOS, since there are only two transistors stacked-up between supply rails. Thus the supplying voltage of this circuit class is the lowest possible one for any particular CMOS technology. The operation principle based on symbolic analysis with simple square model has been fully confirmed by simulations with BSIM3v3 models provided by different silicon foundries and verified experimentally using one of them.     

一种基于0.18μm CMOS工艺的上电复位电路

介绍了一种采用0.18μm CMOS工艺制作的上电复位电路。为了满足低电源电压的设计要求,采用低阈值电压(约0V)NMOS管和设计的电路结构,获得了合适的复位电压点;利用反馈结构加速充电,提高了复位信号的陡峭度;利用施密特触发器,增加了电路的迟滞效果。电路全部采用MOS管设计,大大缩小了版图面积。该上电复位电路用于一种数模混合信号芯片,采用0.18μm CMOS工艺进行流片。芯片样品电路测试表明,该上电复位电路工作状态正常。     

An 8-Bit 50-MS/s CMOS Digital-Analog Converter

In this paper a new 8-bit 50-M sample/s CMOS digital-to-analog converter (DAC) is presented. The circuit employs 9 operational transconductance amplifiers (OTAs) and CMOS transistors as switching circuit. The proposed DAC is simulated using SPICE simulation program with 1.2 m CMOS technology. Simulation results verify good performance of the circuit.     

A simple wide-band CMOS based true rms-to-dc converter

A simple integrable circuit technique for the realization of a wide bandwidth current-mode CMOS true rms-to-dc converter is proposed. The realization scheme is based on the implicit computation method that makes use of the characteristic of a CMOS squaring circuit, where the transistors are biased in their saturation regions. The conversion circuit consumes very low power due to the bias current of the circuit provided by the root-mean-square current I _RMS. The performance of the proposed circuit is studied through PSPICE simulation and experimental results.     

0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI

A novel 0.8 V CMOS adiabatic differential switch logic (ADSL) circuit using the bootstrap technique for low-voltage low-power VLSI is reported. Using capacitance coupling effects from the bootstrap transistors with the related isolating transistors, this 0.8 VADSL circuit has a 52% smaller propagation delay time, consuming 26% less power as compared to the energy efficient logic circuit.     

3.6 mw low power wireless RF receiver front end using creative current recycle technique

This paper presents the design of low noise amplifier and mixer (LIXER) circuit for wireless receiver front ends using 65 nm CMOS technology. The circuit is implemented with CMOS transistors and uses 65 nm CMOS process. Proposed LIXER circuit achieves a maximum gain of 25 dB and DSB noise figure of 3.5 dB. In the given circuit, current shunt paths had created by using LC tank circuit with transistors Q5 and Q6. By using the creative current recycle technique circuit consumes 3.6 mW power with 1.2 V power supply. The operating frequency of the proposed structure is 2.4 GHz with 25 dB conversion gain and ?13 dBm IIP3. The operating of the receiver front end is 2.4 GHz is used for IEEE 802.11a WLAN, Bluetooth, and ZigBee applications.     

A novel current-mode min–max circuit

This paper presents a new CMOS current mode min?Cmax circuit. The proposed circuit has lower number of transistors, can detect minimum and maximum of the input currents at the same time, shows high precision and has a low cell area. It is designed in 0.25???m standard CMOS technology. Layout of the proposed structure is accomplished to extract the parasitic components, where all the simulations are performed with HSPICE level49 (BSIM3v3) parameters obtained from post layout circuit extraction.     

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.     

Regenerative logic circuits with CMOS transistors

Logic circuits with transfer characteristics in the form of hysteresis, proposed in the paper, consist of two stages. The input stage is a standard CMOS logic circuit (inverter, NAND or NOR); the output stage is a simple flip-flop. The flip-flop consists of two inverters and one pair of CMOS transistors functioning as a resistor. The positive feedback loop is closed through these transistors. In the paper the most important static parameters and conditions of normal operation are analysed in detail.     

Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit

Russian Microelectronics - In this paper, we address the problem of converting a flat CMOS circuit of transistors in the SPICE format into a hierarchical circuit of CMOS gates in the same format....     

低电压Charge-Recovery逻辑电路的设计

提出了一种新的适用于低电压工作的 sem i- adiabatic逻辑电路—— Dual- Swing Charge- Recovery L ogic(DSCRL) .该电路由 CMOS- latch- type电路及负载驱动电路构成 ,对负载的驱动为 full- adiabatic过程 .DSCRL 的电源为六相双峰值脉冲电源 ,低摆幅脉冲用于驱动负载 ,高摆幅脉冲用于驱动 CMOS- latch- type电路 .降低负载上摆幅时驱动负载的 NMOS管的栅压可以保持不变 ,有效地解决了传统的 adiabatic电路在低电压工作时 charge- re-covery效率降低的问题 .文中比较了 DSCRL 电路与部分文献中的 semi- adiabatic电路的功耗 ,DSCRL 在低电压工作方面     

A perspective on CMOS technology trends

Integrated circuit technology continues to evolve at a rapid pace, driven by the requirements of new applications for electronics of higher performance at ever lower cost. The attributes of CMOS technology in a ULSI environment are an ideal match to these requirements; thus CMOS is becoming the ubiquitous integrated circuit technology. The main feature of CMOS is the existence of complementary n- and p-channel transistors, which results in circuit configurations with virtually zero steady-state current, and consequently low power dissipation. Although CMOS is conceptually a circuit technology, this has implications for fabrication and layout, as well as for functional partitioning in the circuit design environment and test. These considerations are reviewed with special attention to those areas, such as test, latchup, and the design environment, where technical problems are substantial.     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

一种输出可调CMOS能隙基准源电路的设计

从分析典型的能隙基准电路的一般原理入手，重点讨论了一种输出可调节的CMOS能隙基准电路的设计。通过增加一些辅助电路，提高了电路的电源抑制比。简单介绍了电路中双极晶体管在CMOS工艺中的实现方法。所设计的电路具有输出可调的功能和良好的温度特性。     

Characterization of parasitic transistors to evaluate CMOS processuniformity

The design and fabrication of several families of parasitic transistors available in a standard CMOS process are discussed and their application to process control examined. These transistors are characterized and their extracted parameters correlated with those obtained from CMOS devices. From these correlations it is concluded that parasitic transistors are very sensitive to changes in the process that influence the performance of MOS transistors. As a result parasitic transistors can be used in conjunction with standard MOS devices and test structures to provide a more complete picture of CMOS process variation     

CMOS two-quadrant multiplier using transistor triode regime

A CMOS two-quadrant multiplier using a differential pair with controlled current tail is described. A bias circuit with output current proportional to the square of input voltage provides the tail current for the pair. This bias circuit includes an operational amplifier and two nested transistors. One of these transistors is in pinch-off, the other in the triode region of operation. The transistor mismatch and body effect influence are evaluated. The circuit is verified experimentally