Scaling System-Level Science: Scientific Exploration and IT Implications

The study and creation of the infrastructure required to enable system-level science--the integration of diverse sources of knowledge about the constituent parts of a complex system with the goal of obtaining an understanding of the system's properties as a whole--is becoming increasingly important, spawning new knowledge in variety of fields at a rapid pace.     

A Quality-Driven Design Approach for NoCs

Editor's note:This article advocates a systematic approach to improve NoC design quality by guiding architectural choices according to the difficulty of verification and test. The authors propose early quality metrics for added test, monitoring, and debug hardware.—Yatin Hoskote, Intel     

SoC系统级设计方法与技术

介绍了以Y图为中心的系统级设计方法研究主题,从软硬件协同设计技术、设计重用技术以及与底层相结合设计技术3方面探讨了系统级关键设计技术的研究进展.从设计方法和技术路线上,将当前的研究工作归纳为基于SpecC自顶向下细化求精的设计方法、基于组件多处理器核SoC自底向上搭积木的设计方法和基于平台上下结合分而治之的设计方法3类.在此基础上,对各类方法的基本思想、描述语言、设计模型和关键技术等进行了分析与对比,并给出了该领域存在的研究问题及其今后的研究方向和重点.     

Metamodeling: An Emerging Representation Paradigm for System-Level Design

Editor's note:The use of metamodeling in system design allows abstraction of concepts germane to a number of varying modeling domains, and provides the ability of exploiting meta-information for a variety of system design tasks such as analysis, verification, synthesis, and test generation. This article provides an overview of emerging metamodeling techniques and their applications.—Tim Cheng, IEEE Design & Test editor in chief     

System-Level Fault Diagnosis

Large multiprocessor networks require system-level fault diagnosis. Researchers have established and extended a model for such diagnosis.     

Logic-Based Distributed Routing for NoCs

The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are usually proposed for NoCs, heterogeneous cores, manufacturing defects, hard failures, and chip virtualization may lead to irregular topologies. In this context, efficient routing becomes a challenge. Although switches can be easily configured to support most routing algorithms and topologies by using routing tables, this solution does not scale in terms of latency and area. We propose a new circuit that removes the need for using routing tables. The new mechanism, referred to as Logic-Based Distributed Routing (LBDR), enables the implementation in NoCs of many routing algorithms for most of the practical topologies we might find in the near future in a multicore chip. From an initial topology and routing algorithm, a set of three bits per switch output port is computed. By using a small logic block, LBDR mimics (demonstrated by evaluation) the behavior of routing algorithms implemented with routing tables. This result is achieved both in regular and irregular topologies. Therefore, LBDR removes the need for using routing tables for distributed routing, thus enabling flexible, fast and power-efficient routing in NoCs.     

Bringing NoCs to 65 nm

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The experimental results from fully working 65-nm NoC designs and a detailed scalability analysis are presented. The network on chip (NoC) is a promising solution to the scalability problem. NoCs build upon improvements in bus architecture-for example, in terms of topology design.     

Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs

Network congestion has a negative impact on the performance of on-chip networks due to the increased packet latency. Many congestion-aware routing algorithms have been developed to alleviate traffic congestion over the network. In this paper, we propose a congestion-aware routing algorithm based on the Q-learning approach for avoiding congested areas in the network. By using the learning method, local and global congestion information of the network is provided for each switch. This information can be dynamically updated, when a switch receives a packet. However, Q-learning approach suffers from high area overhead in NoCs due to the need for a large routing table in each switch. In order to reduce the area overhead, we also present a clustering approach that decreases the number of routing tables by the factor of 4. Results show that the proposed approach achieves a significant performance improvement over the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms.     

Guest Editors' Introduction: Tackling Key Problems in NoCs

This special issue highlights recent innovations in network on a chip (NoC) design. The four articles fall into two main thrusts: the first three focus on design methodology challenges in NoCs; the final article demonstrates a practical case study implementation of an NoC.     

Lightweight Transactional Memory systems for NoCs based architectures: Design,implementation and comparison of two policies

Hardware Transactional Memory (HTM) is an attractive design concept which simplifies parallel programming by shifting the problem of correct synchronization between threads to the underlying hardware memory system.     

A Communication-Driven Routing Technique for Application-Specific NoCs

Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the reduction of both area and power dissipation. As a result, two-dimensional meshes have become the preferred topology, since it offers low and constant link delay. Unfortunately, manufacturing defects or even real-time failures often make the resulting topology to become irregular, preventing the use of traditional routing algorithms. This scenario shows the need for topology-agnostic routing algorithms that provide a valid routing solution when applied over any topology. This paper proposes a new communication-driven routing technique that optimizes the network performance for Application-Specific NoCs. This technique combines a flexible, topology-agnostic routing algorithm with a communication-aware mapping technique that matches the traffic generated by the application with the available network bandwidth. Since the mapping technique can be pruned as needed in order to fit either quality function values or time constraints, this technique can be adapted to fit with different computational costs. The evaluation results show that it significantly improves network performance in terms of both latency and power consumption.     

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

DWP, a new interconnect structure for asynchronous networks on chip in multiprocessing SoCs, yields higher throughput, consumes less power, suffers less from crosstalk noise, and requires less area than traditional interconnect structures. Its advantages stem from techniques including wave pipelining, double-data-rate transmission, interleaved lines, misaligned repeaters, and clock gating.     

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment.     

Specifying and Analysing System-Level Inter-Component Interfaces

In control systems, the interfaces between software and its embedding environment are a major source of costly errors. For example, Lutz reported that 20–35% of the safety-related errors discovered during integration and system testing of two spacecraft were related to the interfaces between the software and the embedding hardware. Also, the software’s operating environment is likely to change over time, further complicating the issues related to system-level inter-component communication. In this paper we discuss a formal approach to the specification and analysis of inter-component communication using a revised version of RSML (Requirements State Machine Language). The formalism allows rigorous specification of the physical aspects of the inter-component communication and forces encapsulation of communication-related properties in well-defined and easy-to-read interface specifications. This enables us both to analyse a system design to detect incompatibilities between connected components and to use the interface specifications as safety kernels to enforce safety constraints.     

DATE 07 workshop on diagnostic services in NoCs

The Workshop on Diagnostic Services in Network-on-Chips, held during DATE 2007, focused on test, debugging, and online monitoring in NoCs. The main body of the workshop was formed by two sessions with full-length paper presentations and two lively poster sessions with a total of 28 posters. EPFL's Giovanni De Micheli gave the keynote address, and the workshop also featured a panel session led by Tensilica's Grant Martin and invited talks by Virage Logic's Yervant Zorian and NXP Semiconductors' Kees Goossens. The workshop produced electronic online proceedings, including papers, slides, and posters-totaling 420 pages.     

Communication modeling of multicast in all-port wormhole-routed NoCs

Multicast is one of the most frequently used collective communication operations in multi-core SoC platforms. Bus as the traditional interconnect architecture for SoC development has been highly efficient in delivering multicast messages. Since the bus is non-scalable, it can not address the bandwidth requirements of the large SoCs. The networks on-chip (NoCs) emerged as a scalable alternative to address the increasing communication demands of such systems. However, due to its hop-to-hop communication, the NoCs may not be able to deliver multicast operations as efficiently as buses do. Adopting multi-port routers has been an approach to improve the performance of the multicast operations in interconnection networks. This paper presents a novel analytical model to compute communication latency of the multicast operation in wormhole-routed interconnection networks employing asynchronous multi-port routers scheme. The model is applied to the Quarc NoC and its validity is verified by comparing the model predictions against the results obtained from a discrete-event simulator developed using OMNET++.     

System-Level Performance Metrics for Multiprogram Workloads

Assessing the performance of multiprogram workloads running on multithreaded hardware is difficult because it involves a balance between single-program performance and overall system performance. This article argues for developing multiprogram performance metrics in a top-down fashion starting from system-level objectives. The authors propose two performance metrics: average normalized turnaround time, a user-oriented metric, and system throughput, a system-oriented metric.     

面向非规则三维片上网络的自适应可靠路由方法

面向存在永久性链接故障的非规则三维片上网络,提出一种低成本自适应可靠路由方法.首先根据非规则三维片上网络的拓扑结构,优先选择一条汉密尔顿路径进行容错路由,在没有汉密尔顿路径的情况下,则执行生成树容错路由算法绕过故障链接;然后将基于动态规划的端口选择机制拓展到三维空间,结合前述路由算法来避开网络冲突区域,完成将数据包由源路由器节点传输至目的路由器节点的路由过程.实验结果表明,与之前的AFRA方法和基于生成树的可靠路由方法相比,该方法具有较高的通信性能和可靠性,同时所需的网络开销较低.