Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

Investigation of Au/Ti/Al ohmic contact to N-type 4H–SiC

In this study, investigation on Au/Ti/Al ohmic contact to n-type 4H–SiC and its thermal stability are reported. Specific contact resistances (SCRs) in the range of 10⁻⁴–10⁻⁶ Ω cm², and the best SCR as low as 2.8 × 10⁻⁶ Ω cm² has been generally achieved after rapid thermal annealing in Ar for 5 min at 800 °C and above. About 1–2 order(s) of magnitude improvement in SCR as compared to those Al/Ti series ohmic systems in n-SiC reported in literature is obtained. XRD analysis shows that the low resistance contact would be attributed to the formation of titanium silicides (TiSi₂ and TiSi) and Ti₃SiC₂ at the metal/n-SiC interface after thermal annealing. The Au/Ti/Al ohmic contact is thermally stable during thermal aging treatment in Ar at temperature in the 100–500 °C range for 20 h.     

Ultra-shallow junction formation by spike annealing in a lamp-based or hot-walled rapid thermal annealing system: effect of ramp-up rate

Ultra-shallow p-type junction formation has been investigated using 1050°C spike anneals in lamp-based and hot-walled rapid thermal processing (RTP) systems. A spike anneal may be characterized by a fast ramp-up to temperature with only a fraction of a second soak-time at temperature. The effects of the ramp-up rate during a spike anneal on junction depth and sheet resistance were measured for rates of 40, 70 and 155°C/s in a lamp-based RTP, and for 50 and 85°C/s in a hot-walled RTP. B⁺ implants of 0.5, 2 and 5 keV at doses of 2×10¹⁴ and 2×10¹⁵ cm⁻² were annealed. A significant reduction in junction depth was observed at the highest ramp-up rate for the shallower 0.5-keV B implants, while only a marginal improvement was observed for 2- and 5-keV implants. It is concluded that high ramp-up rates can achieve the desired ultra-shallow junctions with low sheet resistance but only when used in combination with spike anneals and the lowest energy implants.     

Influence of rapid thermal annealing on morphological and electrical properties of RF sputtered AlN films

Aluminum nitride films were deposited, at 200 °C, on silicon substrates by RF sputtering. Effects of rapid thermal annealing on these films, at temperatures ranging from 400 to 1000 °C, have been studied. Fourier transform infrared spectroscopy (FTIR) revealed that the characteristic absorption band of Al–N, around 684 cm⁻¹, became prominent with increased annealing temperature. X-ray diffraction (XRD) patterns exhibited a better, c-axis, (0 0 2) oriented AlN films at 800 °C. Significant rise in surface roughness, from 2.1 to 3.68 nm, was observed as annealing temperatures increased. Apart from these observations, micro-cracks were observed at 1000 °C. Insulator charge density increased from 2×10¹¹ to 7.7×10¹¹ cm⁻² at higher temperatures, whereas, the interface charge density was found minimum, 3.2×10¹¹ eV⁻¹cm⁻², at 600 °C.     

Hydrogen incorporation, diffusivity and evolution in bulk ZnO

Hydrogen is readily incorporated into bulk, single-crystal ZnO during exposure to plasmas at moderate (100–300°C) temperatures. Incorporation depths of >25 μm were obtained in 0.5 h at 300°C, producing a diffusivity of 8 × 10⁻¹⁰ cm²/V s at this temperature. The activation energy for diffusion is 0.17 ± 0.12 eV, indicating an interstitial mechanism. Subsequent annealing at 500–600 °C is sufficient to evolve all of the hydrogen out of the ZnO, at least to the sensitivity of Secondary Ion Mass Spectrometry (<5 × 10¹⁵ cm⁻³). The thermal stability of hydrogen retention is slightly greater when the hydrogen is incorporated by direct implantation relative to plasma exposure, due to trapping at residual damage.     

Low temperature processed hafnium oxide: Structural and electrical properties

In this work hafnium oxide (HfO₂) was deposited by r.f. magnetron sputtering at room temperature and then annealed at 200 °C in forming gas (N₂+H₂) and oxygen atmospheres, respectively for 2, 5 and 10 h. After 2 h annealing in forming gas an improvement in the interface properties occurs with the associated flat band voltage changing from −2.23 to −1.28 V. This means a reduction in the oxide charge density from 1.33×10¹² to 7.62×10¹¹ cm⁻². After 5 h annealing only the dielectric constant improves due to densification of the film. Finally, after 10 h annealing we notice a degradation of the electrical film's properties, with the flat band voltage and fixed charge density being −2.96 V and 1.64×10¹² cm⁻², respectively. Besides that, the leakage current also increases due to crystallization. On the other hand, by depositing the films at 200 °C or annealing it in an oxidizing atmosphere no improvements are observed when comparing these data to the ones obtained by annealing the films in forming gas. Here the flat band voltage is more negative and the hysteresis on the C–V plot is larger than the one recorded on films annealed in forming gas, meaning a degradation of the interfacial properties.     

ICP-induced defects in GaN characterized by capacitance analysis

The defects induced by inductively coupled plasma reactive ion etching (ICP-RIE) on a Si-doped gallium nitride (GaN:Si) surface have been analyzed. According to the capacitance analysis, the interfacial states density after the ICP-etching process may be higher than 5.4 × 10¹² eV⁻¹ cm⁻², compared to around 1.5 × 10¹¹ eV⁻¹ cm⁻² of non-ICP-treated samples. After the ICP-etching process, three kinds of interfacial states density are observed and characterized at different annealing parameters. After the annealing process, the ICP-induced defects could be reduced more than one order of magnitude in both N₂ and H₂ ambient. The H₂ ambient shows a better behavior in removing ICP-induced defects at a temperature around 500 °C, and the interfacial states density around 2.2 × 10¹¹ eV⁻¹ cm⁻²can be achieved. At a temperature higher than 600 °C, the N₂ ambient provides a much more stable interfacial states behavior than the H₂ ambient.     

Optimization of electric properties of high-k zirconium dioxide by varying deposition and annealing conditions

ZrO₂ thin films with a smooth surface were synthesized on silicon by atomic vapor deposition™ using Zr[OC(CH₃)₃]₄ as precursor. The maximum growth rate (7 nm min⁻¹) and strongest crystalline phase were obtained at 400 °C. The increase of the deposition temperature reduced the deposition rate to 0.5 nm min⁻¹ and changed the crystalline ZrO₂ phase from cubic/tetragonal to monoclinic. These films showed no enhancement of the dominating monoclinic phase by annealing. The values of the dielectric constant (up to 32) and leakage current density (down to 1.2×10⁻⁶ A cm⁻² at 1×10⁶ V cm⁻¹) varied depending on the deposition temperature and film thickness. The midgap density of interface states was N_it=5×10¹¹ eV⁻¹ cm⁻². The leakage current and the density of interface states were lowered by the annealing to 10⁻⁷ A cm⁻² at 1×10⁶ V cm⁻¹ and to 10¹⁰ eV⁻¹ cm⁻², respectively. However, this also led to a decrease of the dielectric constant.     

Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

DLTS characterisation of InGaAlP films grown using different V/III ratios

Deep levels in InGaAlP films grown using two different V/III ratios have been studied by employing deep level transient spectroscopy (DLTS). The two samples investigated have the same composition of (Al_0.3Ga_0.7)_0.51In_0.49P and a film thickness of 0.6 μm, but grown with V/III ratios 75 and 50. Two defect levels with activation energies 0.23 and 0.78 eV are detected by temperature-scan DLTS in the sample with a V/III ratio of 75, with the 0.78 eV level being the dominant peak. Their respective capture cross-sections are 1.2×10⁻¹⁶ and 3.8×10⁻¹³ cm⁻². The 0.78 eV trap level is also analysed using isothermal DLTS measurement and similar values of thermal signatures are obtained. The DLTS spectrum of the 0.78 eV trap level has been found to be broader than that expected for a point-type defect, implying that it may be associated with a complex or extended defect. The observation of logarithmic capture mechanism further supports this speculation. On the other hand, no peak corresponding to the 0.23 eV level appears in isothermal DLTS spectra, which is possibly due to the severe temperature dependence of capture rate and the system's limitation in the high-frequency regime. For the sample with a V/III ratio of 50, only one dominant electron trap level, with an activation energy of 0.42 eV and a capture cross-section of 1.4×10⁻¹⁷ cm⁻², is detected by isothermal DLTS method.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Effect of annealing on the properties of low-k nanoporous SiO2 films prepared by sol–gel method with catalyst HF

Using hydrofluoric acid (HF) as catalyst, nanoporous SiO₂ thin film was synthesized by sol–gel method. By scanning electron microscopy, Fourier transform infrared spectra, thermo gravimetric and differential thermal analysis, ellipsometry, capacitance–voltage and current–voltage measurements, the effects of annealing on film properties were discussed in detail. The introduction of HF results in the less polarizability, the preferable microstructures and the improved thermal stability of the nanoporous silica films. After thermal annealing at 450 °C, the crack-free films with strong hydrophobicity, ultra-low dielectric constant of 1.65, porosity of 78%, and leakage current density of 1.3 × 10⁻⁸ A cm⁻² were obtained.     

Charge trapping characterization of MOCVD HfO2/p-Si interfaces at cryogenic temperatures

The paper focuses on the study of charge trapping processes in high-k MOS structures at cryogenic temperatures. It was shown, that there is extremely strong trapping in shallow electron and hole traps, localized in the high-k dielectrics. Concentration of shallow electron traps is as much as 10¹³ cm⁻², while abnormal small capture cross-sections (4.5–8 × 10⁻²⁴ cm² for different samples, accordingly) suggests localization of shallow emitting electron traps in transition layer “high-k dielectric/Si”, more, than at the interface. Shallow hole traps with concentration near 10¹² cm⁻² are separated from silicon valence band with energy barrier in the range 10–39 meV for different samples.     

Optical and electrical characterization of the electron beam gun evaporated TiO2 film

We report measured evolutions of the optical band gap, refractive index and relative dielectric constant of TiO₂ films obtained by electron beam gun evaporation and annealed in an oxygen environment. A negative shift of the flat band voltage with increasing annealing temperatures, for any film thickness, is observed. A dramatic reduction of the leakage current by about four orders of magnitude to 5×10⁻⁶ A cm⁻² (at 1 MV cm⁻¹) after 700°C and 60 min annealing is found for films thinner than 15 nm. The basic carrier transport mechanisms at different ranges of applied voltage such as hopping, space charge limited current and Fowler–Nordheim is established. An equivalent SiO₂ thickness in order of 3.5 nm is demonstrated.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

Control of Ga doping level in β-FeSi2 using Sn–Ga solvent

We have grown n- and p-type β-FeSi₂ single crystals by the temperature gradient solution growth method using Sn–Ga solvent. The conduction type and the carrier density of the crystals were controlled by the Ga composition in the Sn–Ga solvent. The conduction type was changed from n- to p-type between the Ga composition of 10.2 and 18.5 at% in the solvent. Depending on the Ga composition in the solvent, the carrier density of n- and p-type crystals was changed from 1.5×10¹⁷ to 3×10¹⁷ cm⁻³ and 4×10¹⁷ to 2×10¹⁹ cm⁻³, respectively. The activation energies of n-type crystals were 0.09–0.11 eV while that of p-type crystals were 0.02–0.03 eV.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

Properties of Bi-doped PbTe epitaxial layers and pn junction diodes grown by TDM-CVP

Effects of Bi-doping in PbTe liquid-phase epitaxial layers grown by the TDM-CVP have been investigated. For Bi concentration in the solution, x_Bi, lower than 0.2 at.%, Hall mobility is low. In contrast, for x_Bi>0.2 at.%, Hall mobility is high, while carrier concentration is in the range 10¹⁷ cm⁻³. However, ICP emission analysis shows that, for x_Bi=1.0 at.%, Bi concentration in epitaxial layer is N_Bi=2.3–2.7×10¹⁹ cm⁻³.These results indicate that Bi behaves not only as a donor but also as an acceptor; the nearest neighbor or very near DA pairs are formed. Carrier concentration for Bi-doped layers takes a minimum value at a Te vapor pressure of 2.2×10⁻⁵ Torr for growth temperature 470°C, which is coincident with that of the undoped PbTe. And broad contact pn junctions with highly Bi-doped layers easily cause laser emission compared to undoped junctions. The result suggests that the nearest lattice site Bi–Bi DA pairs behave as strong radiative centers in PbTe.     

Luminescence and microstructure of Er/O co-doped Si structures grown by MBE using Er and SiO evaporation

Er and O co-doped Si structures have been prepared using molecular-beam epitaxy (MBE) with fluxes of Er and O obtained from Er and silicon monoxide (SiO) evaporation in high-temperature cells. The incorporation of Er and O has been studied for concentrations of up to 2×10²⁰ and 1×10²¹ cm⁻³, respectively. Surface segregation of Er can take place, but with O co-doping the segregation is suppressed and Er-doped layers without any indication of surface segregation can be prepared. Si_1−xGe_x and Si_1−yC_y layers doped with Er/O during growth at different substrate temperatures show more defects than corresponding Si layers. Strong emission at 1.54 μm associated with the intra-4f transition of Er³⁺ ions is observed in electroluminescence (EL) at room temperature in reverse-biased p–i–n-junctions. To optimize the EL intensity we have varied the Er/O ratio and the temperature during growth of the Er/O-doped layer. Using an Er-concentration of around 1×10²⁰ cm⁻³ we find that Er/O ratios of 1 : 2 or 1 : 4 give higher intensity than 1 : 1 while the stability with respect to breakdown is reduced for the highest used O concentrations. For increasing growth temperatures in the range 400–575°C there is an increase in the EL intensity. A positive effect of post-annealing on the photoluminescence intensity has also been observed.