一种多DSP间飞越传输验证平台的实现

介绍了飞越传输在多DSP系统中的应用,提出一种软硬件协同验证平台对多DSP系统中的飞越传输功能进行验证。该协同验证平台能够在设计早期发现系统中的硬件错误和软件错误,提高验证效率。在实际应用中该协同验证平台工作稳定,高效准确地完成了设计验证。     

集成电路设计的系统级描述语言SystemC

人们提出了软件硬件协同设计的设计方法，以克服传统的将软件和硬件分开的设计方法对于SOC的设计存在的缺陷。SyStenlC是顺应这种发展趋势而产生的系统级描述语言。它是一种通过类对象扩展和基于C／C 的建模平台，支持系统级软硬件协同设计、仿真、验证、软硬件协同设计的系统级描述语言。本文介绍了系统级描述语言SySternC在集成电路设计中的应用，讨论了基于SyStemC的集成电路设计的设计流程、设计优势及其发展趋势。     

基于ESL的MEPG-4解码SoC软硬件协同设计

随着SoC(System on Chip)系统设计复杂度的不断提高,设计前期在系统级别进行软硬件规划对SoC 性能的影响日趋增加,在复杂视频解码SoC 设计中迫切需要高效的性能分析和验证平台从架构层次上优化性能.将基于电子系统级设计(Electronic System Level , ESL)仿真方法在MPEG-4 视频解码SoC 软硬件协同设计中的应用,利用ARM SoC-Designer ESL 平台分析软件算法的瓶颈,实现软硬划分.通过SystemC 对硬件单元周期精确建模,最终实现了MEPG-4 解码软硬件协同仿真验证.实践证明利用ESL 进行系统设计不仅可以有效提高仿真速度而且设计的视频解码硬件能有效改善系统的性能.     

一种高效Cable Modem SOC软硬件协同验证平台

通过对基于龙芯一号CPU的双向有线调制解调器SOC的研究,利用软件仿真和硬件模拟相结合的方法,设计了一种软硬件协同验证平台TWCNP,可分别对EuroDOCSIS协议栈、EuroDOCSIS协议处理器、整个双向有线网络SOC等软硬件进行验证,并实现了验证和设计的统一.为了提高TWCNP的验证时效性,提出了一种基于TWCNP-OS的软硬件协同验证方法,缩短了开发周期,保证了SOC设计的可靠性.     

嵌入式系统软硬件协同模拟验证环境设计与实现

介绍了一个嵌入式系统软硬件协同模拟验证环境，该环境以指令集模拟器和事件驱动硬件模拟器为基本框架，并由总线调度模型和总线界面模型提供软硬件模拟交互界面。重点讨论该环境中软硬件模拟器之间的接口设计与实现方法，最后给出一个嵌入式系统协同验证的应用实例。     

大规模SoC设计中的高效FPGA验证技术的研究与实现

一种针对大规模SoC设计的高效FPGA验证流程,分析了该流程所涉及的关键技术:通用硬件平台设计、FPGA软件环境设计和软硬件协同验证等。采用这些技术,FPGA平台可以快速且真实地模拟芯片应用平台,从而实现软硬件并行设计和协同验证。该验证流程已灵活应用于大规模SoC项目设计中,大大提高了SoC产品的研发效率。     

星载计算机软硬件协同验证技术的研究

在星载计算机LYRA的设计和验证过程中,采用System Verilog的DPI建立了完整的、低成本的、高效的SOC系统软硬件协同验证的系统仿真平台;利用这种技术使得可以在实际硬件可用前进行C/C++代码的开发和测试,同时又可以利用真实的软件对硬件进行验证;在早期软硬件可以公用测试平台进行并行开发,不仅大大减少软硬件开发的重复工作,加快了验证速度,还能对软硬件之间的边角情况进行完整的验证;验证方法已经成功的应用于星载计算机LYRA的开发中,取得了良好的效果。     

基于SystemC的嵌入式系统软硬件协同设计

提出了一种基于SystemC的嵌入式系统软硬件协同设计方法。SystemC是OSCI(OpenSystemCIni tiative)组织制定和维护的一种开放源代码的C 建模平台 ,提供支持硬件建模和仿真的C 类库及相应的仿真内核。通过SystemC的支持 ,该方法在整个嵌入式系统设计流程内使用C 语言来统一描述硬件和软件 ,实现软硬件的协同设计和仿真。该方法同传统的设计方法相比更加灵活和有效。     

基于多代理系统的软硬件协同设计

为使软硬件协同设计过程更具分布性、自主性及并行性,在软硬件协同设计中引入多代理(MAS)技术,提出软硬件协同设计的MAS模型,包括系统描述Agent、软硬件划分及映射Agent、软硬件设计Agent、协同通信Agent、性能评估Agent和硬件系统测试Agent的构建和应用。采用多个目标代理映射、协商的方法协调整个协同设计过程。实际应用表明,该方法能优化系统级芯片设计方案、软硬件结构和功能,并提高系统整体性能。     

H.264高清编码器系统的设计与仿真

常用软件编码方法在用于H.264标准时,很难实现对高清视频的实时解码。为此,提出软硬件协同设计的方法,对H.264高清编码器系统进行软硬件划分及任务分配,分别设计软件部分和硬件部分。建立软硬件协同仿真环境,对整个系统的功能和性能进行仿真,采用约束随机验证的方法提高验证的功能覆盖率。仿真结果表明,该编码器系统能够对 1 024×768像素的图像帧进行编码,满足实时编码的要求。     

A metaprogrammed C++ framework for hardware/software component integration and communication

With the ever growing complexity of System-on-Chip design, a considerable effort has been made to introduce higher levels of abstraction and to integrate high-level synthesis solutions to the design flow. In such design flows, a uniform communication interface is needed to enable high-level implementations of SoC components regardless of whether they are compiled as software running on a processor or synthesized to dedicated hardware IPs. This paper addresses this issue and proposes a component communication framework that defines an object-oriented remote call mechanism which allows transparent communication across hardware/software boundaries. The proposed framework relies on C++ static metaprogramming techniques to efficiently abstract communication between components implemented using high-level C++. We also define a portability layer that enables the migration of designs throughout different hardware platforms, operating systems, and tools. We assessed the performance and area footprint of our communication infrastructure through the implementation of a voice processing pipeline on top of a Network-on-Chip based architecture. Our results, when compared to previous related works with the same set of capabilities, show that our mechanisms yield small overhead in terms of software memory (up to 64% smaller), FPGA resources (up to 40% smaller), and hardware/software communication latency (up to 51% smaller).     

过程级动态划分的RSoC软硬件双通信模式

软硬件通信模式的选择对软硬件通信效率产生很大影响.根据硬件函数的特点,提出一种根据软硬件通信量自适应地选择通信模式的软硬件双通信模式,并构建了一种通信模式自适应决策算法,软硬件通信模式的选择对用户透明.实验表明,根据运行时系统状态自适应地选择通信模式,软硬件通信效率得到优化,面积开销也适当减少.     

基于虚拟微处理器的嵌入式软件开发与系统验证环境

嵌入式系统设计过程中软件与硬件集成验证的滞后，已成为制约整个系统开发进程的重要因素．虚拟微处理器是指在嵌入式系统硬件原型形成之前构造的可仿真原型，通过对微处理器的仿真支持软件嵌入式软件开发．介绍了基于虚拟微处理器技术的嵌入式软件开发环境的设计和实现，利用该环境，设计者可在设计早期进行系统集成验证，减少设计错误并缩短设计周期．该环境已经在嵌入式系统开发过程中得到成功应用．     

一种基于SoC平台设计的AVS解码器软硬件分区结构

视频解码芯片的结构因硬件强大的处理能力和软件灵活的可编程功能从硬件转向软硬件分区结构。该文针对AVS标准的算法和解码实现复杂程度,根据软硬件协同设计思想提出了一种结构划分合理的AVS高清视频解码器软硬件分区结构。根据AVS算法的特点该结构将宏块层以上部分的元素解析划归到软件解码中,将宏块层解码划为硬件处理。经验证,该结构设计可实现AVS高清码流解码,并在C语言编写的硬件平台仿真程序中得以实现。     

基于平台和中间件的嵌入式系统软硬件协同设计

提出了一种基于平台和软件中间件技术的嵌入式系统软硬件协同设计方法。通过显微图像嵌入式Internet技术的具体研究,比较详细地分析了嵌入式系统软硬件协同设计方法,并给出设计流程。通过软/硬件平台的设计,以及TCP/IP协议栈等中间件的具体开发,实现了一个实用的嵌入式系统,并给出实验测试结论。研究结果表明:该方法有利于复杂系统的层次化分解、软件复用,以及软硬件优化,同时,可提高系统的可靠性。是一种有效的嵌入式系统设计方法。     

Parallel Programming of Multi-processor SoC: A HW–SW Interface Perspective

For the design of classic computers the parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs.     

基于可配置处理器的SoC系统级设计方法

论文对一种经过改进的SoC系统级快速设计方法进行了介绍和研究。该设计基于可配置处理器核,在设计早期阶段对SoC系统快速建模,以获得针对具体应用算法的最优性能。同时,利用软硬件协同设计方法,得到硬件结构模型和软件开发平台。实验结果表明,该方法不仅灵活,而且设计周期短,减少了设计工作量。     

C语言系统描述的HCDFG-Ⅱ实现

C语言是系统设计中一种主要的系统描述语言，在系统级软硬件协同验证及随后的软硬件划分、接口综合和行为综合等中都需要把C语言的系统描述转化为控制数据流图。本文介绍了一种层次化控制数据流图HCDFG-Ⅱ模型，以及从C语言生成该模型的方法。HCDFG-Ⅱ的层次化模型分为函数／进程级、语句级和操作级，根据需要可以生成不同级别的模型。本文讨论了C语言中各种控制结构及数组、指针、联合和结构等复杂数据类型生成HCDFG-Ⅱ的方法。     

Interfacing the hardware API with a feature-based operating system family

Multiprocessor systems on a chip (MPSoCs) are a popular class of course-grained parallel computer architectures, which are very useful, because they support re-use of legacy software components and application-specific tailoring of hardware structures at the same time. Furthermore, model-driven design frameworks for MPSoCs such as Xilinx’ EDK or our own LavA-framework facilitate very fast system development. However, in this paper we argue that these design frameworks are not ideal from the development process perspective. Instead, we propose a software-centric approach that is based on the hardware API concept. The API is a representation of hardware components on the software level, which is generated from a hardware meta-model. It allows us to automatically derive a hardware structure based on access patterns in software, revealed by a static code analysis. This trick reduces the number of hardware details the developer needs to deal with and avoids configuration inconsistencies between the hardware and software levels by design. Furthermore, we present how the development process can benefit from the hardware API, when the API is interfaced with a configurable operating system.     

An FPGA Design for Real-Time Image Denoising

The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part. The SW part is developed based on C/C++ programming language and executed on an advanced reduced instruction set computer (RISC) machines (ARM) Cortex-A53 processor. The communication between the SW and HW parts is achieved using the advanced extensible Interface stream (AXI-stream) interface to increase the data bandwidth. The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98% for the HW/SW implementation relative to the SW implementation. This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference (NCD) and the peak signal to noise ratio (PSNR).