Mo/Al metallization for VLSI applications

We have investigated the ohmic contact properties of a metallization system made of a thin ( < 50-nm) film of aluminum covered by a thick (≈ 0.4-µm) layer of molybdenum. The thin aluminum film provides good contact characteristics to shallow n⁺-p and p⁺-n junctions in silicon, and good adherence. The thick molybdenum overlayer, which is the primary current carrier, contributes good thermal and metallurgical reliability features. Results of the present study show that the combined Mo/Al metallization system is suitable for use in very large scale integrated circuits, as the first-level metallization in a multilevel interconnect scheme.     

Planarization of gold and aluminum thin films using a pulsed laser

Micrometer-thick gold and aluminum films have been planarized by momentarily melting them with optical pulses from a dye laser. Submicrosecond pulses were used in order to minimize the temperature rise in the substrate, reduce the energy required for melting, and prevent undesirable metallurgical reactions. Planarization of two-level gold metallization structures insulated by SiO2(including interlevel vias) has been achieved. Aluminum metallization on integrated circuits (IC's) has also been planarized. The use of a thin (<200 Å) silicon overcoating greatly aids the aluminum planarization process by passivating the aluminum and increasing its initial optical absorbance.     

集成电路芯片上光互连研究的新进展

讨论了集成电路向高集成度、高工作频率和高传输速率继续发展时,常规金属互连出现的困难以及集成电路芯片上光互连具有的潜在优势．介绍了组成芯片上光互连的光发射器件、光接收器件和光传输器件等三种基本器件及其与硅集成电路集成的研究新进展．最后展望了集成电路芯片上光互连的应用前景．     

集成电路芯片上光互连研究的新进展

讨论了集成电路向高集成度、高工作频率和高传输速率继续发展时 ,常规金属互连出现的困难以及集成电路芯片上光互连具有的潜在优势 .介绍了组成芯片上光互连的光发射器件、光接收器件和光传输器件等三种基本器件及其与硅集成电路集成的研究新进展 .最后展望了集成电路芯片上光互连的应用前景 .     

Advancements in bipolar VLSI circuits and technologies

Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic and emitter-coupled logic are still mostly used, but new circuit technologies such as integrated injection logic or merged transistor logic and Schottky transistor logic or integrated Schottky logic have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly being replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected through technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 /spl mu/m dimensions or below.     

A highly flexible sea-of-gates structure for digital and analogapplications

A sea-of-gates structure optimized for digital random logic applications as well as for regular arrays and analog circuits is described. Associated with a dedicated design procedure and a systematic metallization strategy, the structure features a full cell-abutment capability and true channelless routing. After reviewing the advantages and limitations of currently available arrays, the main characteristics of the array architecture are presented, and applications to different circuit families are detailed. Design automation tools suited to the structure and design methodology are reviewed. Design results and performance are presented for several macroblocks and are compared with other semicustom approaches. A set of rules which allows an automatic transformation of the sea-of-gates layout into a topologically equivalent full-custom layout, converting semicustom prototypes to full-performance circuits, is presented     

Laser linking of metal interconnects: analysis and designconsiderations

Lateral connections between adjacent lines of metallization have been developed in order to achieve high density linking for customization in programmable gate arrays and for additive redundancy in restructurable integrated circuits. Links were formed by focusing a pulsed laser between two same-level aluminum lines. The mechanism of link formation appears to be the nucleation of a fissure, induced by the thermal expansion mismatch between the metallization and the surrounding dielectric (SiO₂) and passivation layer (Si₃N₄); molten aluminum fills the crack. Numerical simulation by the finite element method was carried out using a plane strain model. The probable path for the link-forming fissure, as predicted by the model on the premise that the local maximum tensile stress determines cracking, is shown to be consistent with experimental observations. Parametric analyses were performed to gain insights into the linking processes. It is found that damage in the passivation can be avoided by increasing the thickness of the dielectric between the aluminum and the passivation. Reducing the spacing between the metal lines increases the chance of successfully forming the link. Under certain conditions, the linking propensity can also be increased by reducing the metal width. In addition, the link is much easier to form when symmetric laser heating between the two metal lines can be achieved. These findings can be directly applied to improving the design of the laser linking processes and devices     

Study of the step coverage and contact resistance by using two-step TiN barrier and evolve simulation

Device aspect ratios and dimensions at the contact and via levels for old and new technologies are driving PVD/WCVD-based metallization to its full limit at integrated circuits (ICs) fabrication sites (Wilson et al., 1993). Contact and via This work describes the work performed at ST Microelectronics regarding the TiN barrier film properties with respect to process variables. Single-step and dual-step TiN barrier processes were studied for contact and via step coverage profiles used for aluminum and tungsten plug technologies. Electrical contact resistance values were evaluated using single and dual step TiN barrier processes. EVOLVE, a topography simulation program was used to study the step coverages and deposited film profiles for single and dual steps TiN barrier processes. In this work we prove that dual step TiN barrier process is superior to single step TiN barrier process in terms of step coverage, current leakage, film stress and contact resistance values.     

Applications of integrated circuit technology to microwave frequencies

Integration techniques suitable for microwave circuits have been developed. Various aspects of the technology of integration of microwave circuits are reviewed and the reasons for choosing the hybrid approach instead of the monolithic approach and thin-film metallization instead of thick-film are discussed. Design data relating circuit performance to substrate roughness and thickness of thin-film metal adhesion layers are presented. Propagation and radiation characteristics of microstrip lines are discussed. Design equations for thin-film lumped-element passive components are given. Exampies of various microwave integrated circuits are shown.     

Monolithically integrated HgCdTe focal plane arrays

The cost and performance of hybrid HgCdTe infrared (IR) focal plane arrays are constrained by the necessity of fabricating the detector arrays on a CdZnTe substrate. These substrates are expensive, fragile, available only in small rectangular formats, and are not a good thermal expansion match to the silicon readout integrated circuit. We discuss in this paper an IR sensor technology based on monolithically integrated IR focal plane arrays that could replace the conventional hybrid focal plane array technology. We have investigated the critical issues related to the growth of HgCdTe on Si read-out integrated circuits and the fabrication of monolithic focal plane arrays: (1) the design of Si read-out integrated circuits and focal plane array layouts; (2) the low-temperature cleaning of Si(001) wafers; (3) the growth of CdTe and HgCdTe layers on read-out integrated circuits; (4) diode creation, delineation, electrical, and interconnection; and (4) demonstration of high yield photovoltaic operation without limitation from earlier preprocessing such as substrate cleaning, molecular beam epitaxy (MBE) growth, and device fabrication. Crystallographic, optical, and electrical properties of the grown layers will be presented. Electrical properties for diodes fabricated on misoriented Si and readout integrated circuit (ROIC) substrates will be discussed. The fabrication of arrays with demonstrated I–V properties show that monolithic integration of HgCdTe-based IR focal plane arrays on Si read-out integrated circuits is feasible and could be implemented in the third generation of IR systems.     

Electromigration in Double-Layer Metallization

The electromigration of the top stripe in aluminum double-layer metallization systems was investigated. The current density dependence and the activation energy characterization are important in double-layer metallization. The step-coverage and coating effects of SiN is better than that of Si02. New phenomena associated with electromigration have been observed as follows: 1. The mean lifetime is affected by the material of the dielectric layer. This material effect might be related to the hardness of layer. 2. The mean lifetime due to electromigration depends on the magnitude and polarity of the electric field applied between adjacent stripes. Ordinary stress tests for electromigratfon are done where current is conducted only in the top stripe and not in the bottom stripe. Our results show that this situation is realistic under conditions existing in microelectronic circuits. The proposed method for stress testing should be used to simulate actual condition in microelectronic circuits. We emphasize that the stress test method used to disclose this electric field effect is important for accelerated stress testing, especially for metallization in VLSI circuits and multi-layer systems. The failure mechanism due to the electric field effect can be explained in terms of the applied electric field deflecting current-carrying electrons in the metal stripe, and is independent of leakage current between stripes.     

Barrier layers for Cu ULSI metallization

Barrier layers are integral parts of many metal interconnect systems. In this paper we review the current status of barrier layers for copper metallization for ultra-large-scale-integration (ULSI) technology for integrated circuits (ICs) manufacturing. The role of barrier layers is reviewed and the criteria that determine the process window, i.e. the optimum barrier thickness and the deposition processes, for their manufacturing are discussed. Various deposition methods are presented: physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), electroless deposition (ELD), and atomic layer CVD (ALCVD) for barrier layers implementation. The barrier integration methods and the interaction between the barrier and the copper metallization are presented and discussed. Finally, the common inspection and metrology for barrier layer are critically reviewed.     

The tapered slot antenna-a new integrated element formillimeter-wave applications

Tapered slot antennas (TSAs) with a number of potential applications as single elements and focal plane arrays are discussed. TSAs are fabricated with photolithographic techniques and integrated in either hybrid or MMIC circuits with receiver or transmitter components. They offer considerably narrower beams than other integrated antenna elements and have high aperture efficiency and packing density as array elements. Both the circuit and radiation properties of TSAs are reviewed. Topics covered include: antenna beamwidth, directivity, and gain of single-element TSAs; their beam shape and the effect of different taper shapes; and the input impedance and the effects of using thick dielectrics. These characteristics are also given for TSA arrays as are the circuit properties of the array elements. Different array structures and their applications are also described     

Layered and Homogeneous Films of Aluminum and Aluminum/Silicon with Titanium and Tungsten for Multilevel Interconnects

Layered structures and homogeneous alloy films synthesized by sputter deposition were investigated for use in a VLSI multilevel interconnect technology. Major areas studied include hillock formation, resistivity before and after annealing, film composition and structure, reproducibility, interlevel shorts, and dry etching. It has been demonstrated in this work that aluminum alloyed with silicon and titanium and layered with titanium offers advantages over current technological materials for interconnections in integrated circuits. Measurements of surface roughness and electrical shorts between two levels of metal showed that the hillock densities in the films are significantly reduced when small amounts (one to three atomic percent) of titanium and silicon are present. The resistivity of such homogeneous films, however, is 4.5 to 5.5 /spl mu//spl Omega//spl dot/cm, which is higher than standard metallization alloys. When Al/Si was layered with Ti, no hillocks were observed and the resistivity of the composite films was comparable to standard metallization alloys.     

Monolithic LED arrays by selective liquid-phase epitaxy in GaP

Progress in the fabrication of monolithic matrix-addressed arrays of light-emitting diodes (LED's) in GaP using selective liquid-phase epitaxy is reviewed. The structures of two red arrays and one green array are discussed in detail. Photographs of the arrays are shown to demonstrate their capability as alphanumeric displays which may be easily interfaced with silicon integrated circuits. The use of selective liquid-phase epitaxy (LPE) to make flip-chip bonded displays is also discussed.     

Healing of voids in the aluminum metallization of integratedcircuit chips

A thermal treatment for healing voids in the aluminum metallization of integrated circuit (IC) chips has been discovered. The aluminum metallization is alloyed with nominally 1 wt.% of silicon. This discovery arose from efforts to cause further growth of preexisting voids in IC RAMs intended for long-term unattended spacecraft applications. The experimental effort was intended to cause further void propagation for the purpose of establishing a time/temperature propagation relationship, but it resulted instead in a healing of the voids. The thermal treatment consisted of heating IC chips with voids in the aluminum/silicon metallization to temperatures in excess of 200°C, followed by quick immersion into liquid nitrogen. The thermal treatment is described, and a theory based on silicon solubility and migration in aluminum is advanced to explain both the formation and the healing of voids in the aluminum metallization of IC chips     

Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects

Layered structures and homogeneous alloy films synthesized by sputter deposition were investigated for use in a VLSI multilevel interconnect technology. Major areas studied include hillock formation, resistivity before and after annealing, film composition and structure, reproducibility, interlevel shorts, and dry etching. It has been demonstrated in this work that aluminum alloyed with silicon and titanium and layered with titanium offers advantages over current technological materials for interconnections in integrated circuits. Measurements of surface roughness and electrical shorts between two levels of metal showed that the hillock densities in the films are significantly reduced when small amounts (one to three atomic percent) of titanium and silicon are present. The resistivity of such homogeneous films, however, is 4.5 to 5.5 µΩ.cm, which is higher than standard metallization alloys. When Al/Si was layered with Ti, no hillocks were observed and the resistivity of the composite films was comparable to standard metallization alloys.     

The barrier characteristics on silicon of Tixw1-x films of different compositions

An Aluminum/Barrier Layer/Silicide/Silicon contact system is an advanced metallization system used in VLSI. TiW alloy film is one of the barriers that has widely been used in the fabrication of bipolar integrated circuits. In this paper, the barrier characteristics of TiW alloy films of different compositions were studied by means of Auger Electron Spectroscopy (AES). The results indicate that TiW alloy film is indeed an effective barrier to prevent Al-Si interdiffusion if the concentration of Ti is less than 30 at.%.     

High-performance automatic target recognition through data-specificVLSI

Under the Mojave configurable computing project, we have developed a system for achieving high performance on an automatic target recognition (ATR) application through the use of configurable computing technology. The ATR system studied here involves real-time image acquisition from a synthetic aperture radar (SAR). SAR images exhibit statistical properties which can be used to improve system performance. In this paper, the Mojave configurable computing system uses field programmable gate arrays (FPGA's) to implement highly specialized circuits while retaining the flexibility of programmable components. A controller sequences through a set of specialized circuits in response to real-time events. Computer-aided design (CAD) tools have been developed to support the automatic generation of these specialized circuits. The resulting configurable computing system achieves a significant performance advantage over the existing solution, which is based on application specific integrated circuit (ASIC) technology     

Applications of SPICE for modeling miniaturized biomedical sensor systems

This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.