Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

A multistrata dynamic random access memory (DRAM) vertically integrated with a complementary metal oxide semiconductor (CMOS) logic device using through-silicon vias (TSVs) and a unique interposer technology was developed for high-performance, power-efficient, and scalable computing. SMAFTI (SMArt chip connection with FeedThrough Interposer) technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was used for interconnecting the three-dimensionally stacked DRAM and the CMOS logic device . A DRAM-compatible TSV manufacturing process was realized through the use of a “via-first” process and highly doped poly-Si TSVs for vertical traces inside memory dice. A multilayer ultra-thin die stacking process with micro-bump interconnection using a solid-liquid interdiffusion technique was also developed. The thermal aging reliability of the micro-bump interconnection was evaluated by a unique analysis method and its basic reliability was confirmed. Finally, we fabricated a prototype package including stacked DRAM and a CMOS logic device, and observed the combined operation. High-speed 3 Gbit/s signals were successfully transmitted through the fine interposer between the memory and logic.      

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

A 55-ns 16-Mb DRAM with built-in self-test function usingmicroprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm² chip area was attained by implementing 4.05-μm² storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm² and the area overhead is about 1%, it proves to be promising for large-scale DRAMs     

Silicon nitride thin-film deposition by LPCVD with in situ HF vaporcleaning and its application to stacked DRAM capacitor fabrication

Silicon nitride film deposited by LPCVD with newly developed in situ HF vapor cleaning has been studied and applied to fabricate dielectric films for stacked DRAM capacitors. Using this method, an oxide-free surface of underlaid poly-Si can be obtained. Silicon nitride film deposited on this surface has been verified by FTIR measurement to have the stoichiometrically proper composition of Si₃N₄ . However, the film was found to be selectively deposited on poly-Si electrodes. This selective deposition degrades the reliability of the stacked capacitor, because the silicon nitride can not completely cover the periphery of poly-Si electrodes on SiO₂. We propose a simple process that avoids the problem making it possible to apply silicon nitride film to stacked-capacitor fabrication. Stacked capacitors fabricated by this process exhibit very low leakage current and high electrical reliability even for ultra-thin silicon nitride films less than 5 nm thick     

Hidden double data transfer scheme for MDL design [merged DRAMlogic]

A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with logically divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% faster read access. It can be used as a general design framework to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 μm DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory     

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can operate on a 1.8 V power supply as two separate mobile DDR or SDR DRAMs through each channel with maximum data rate of 333 Mbps/pin because of its exclusive accessibility from each channel to memory arrays. Data exchange between two channels is also possible by sharing one common memory array, and a new control scheme of DRAM for this sharing is proposed. The new control scheme is based on direct addressing mode to achieve compatibility with normal DRAM interface together with fast data transfer speed between two channels.      

A 1-Gb DRAM for file applications

A time-shared offset-canceling sensing scheme, a defective word-line Hi-Z standby scheme, and a flexible multimacro architecture have been developed for 1-Gb DRAM. These circuit technologies have been applied to a 1-Gb DRAM for file applications employing 0.25 μm CMOS process technology, a diagonal bit-line cell, and a two-stage pipeline circuit technique. In this DRAM, a 30% chip size reduction and a 400-MB/s data transfer rate have been achieved. A 100% improvement in yield has been estimated by Monte-Carlo simulation. The 1-Gb DRAM die size is 936 mm². The cell size is 0.54 μm². The operating current is 58 mA at 2 V and 100 MHz     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Limitations and challenges of multigigabit DRAM chip design

This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V_T) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-V_T, dynamic V_T, and node-boosting schemes     

A four-level storage 4-Gb DRAM

A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each corresponding to two-bit-data storage in a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier using charge coupling and charge sharing was developed for the four-level sensing and restoring. The sense amplifier uses a hierarchical bit-line scheme and operates in a time-sharing mode, thus reducing the sense amplifier area. A 4-Gb DRAM fabricated using 0.15-μm CMOS technology measures 986 mm². The memory cell is 0.23 μm². Its capacitance of 60 fF is achieved by using a high-dielectric-constant material BST     

三维叠层DRAM封装中硅通孔开路缺陷的模拟

采用硅通孔(TSV)技术的三维堆叠封装,是一种很有前途的解决方案,可提供微处理器低延迟,高带宽的DRAM通道.然而,在3D DRAM电路中,大量的TSV互连结构,很容易产生开路缺陷和耦合噪声,从而导致了新的测试挑战.通过大量的模拟研究.本文模拟了在三维DRAM电路的字线与位线中出现的TSV开路缺陷的故障行为,它作为有效...     

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t_RAS=50 ns (typical) at V_cc=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V_SS shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4-μm CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM     

High-Density Through Silicon Vias for 3-D LSIs

High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.      

A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM

Mobile Wide-I/O DRAMs are used in smartphones, tablets, handheld gaming consoles and other mobile devices. The main benefit of the Wide-I/O DRAM over its predecessors (such as LPDDRx DRAMs) is that it offers more bandwidth at lower power. In this paper, we propose a Wide-I/O DRAM built-in self-test design, named WIO-BIST including the local BIST (LO-BIST), global BIST (GL-BIST) and test interface structures, to support the fault detection in memory-die channels and TSVs. It should be noted that, a TSV test scheme is presented embedding the test procedure of TSVs into the memory-die channel test processes to significantly save the test time of TSVs. A logic die and 4 memory-dies stacking configuration is used to act as a dedicated circuit to demonstrate the feasibility of the proposed WIO-BIST design. Experimental results and comparisons show that the proposed WIO-BIST design has good performance in test time reduction with tiny extra area overhead penalty.     

Superior low-pressure-oxidized Si3N4 films onrapid-thermal-nitrided poly-Si for high-density DRAM's

High-performance stacked storage capacitors with small effective-oxide-thickness (t_ox,eff) as thin as 37 Å has been achieved using low-pressure-oxidized nitride films deposited on NH ₃-nitrided poly-Si electrodes. The capacitors exhibit excellent leakage property and time-dependent dielectric-breakdown (TDDB) characteristics. Furthermore, this technique is promising for the 64- and 256-Mb dynamic-random-access-memory (DRAM) applications because the process temperatures never exceed 850°C     

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

A 3.3-V 512-k×18-b×2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as the conventional DRAM, has been achieved with 0.50-μm CMOS process technology     

Experimental characterization of coaxial through silicon vias for 3D integration

Coaxial through silicon via (TSV) technology is gaining considerable interest as a 3D packaging solution due to its superior performance compared to the current existing TSV technology. By confining signal propagation within the coaxial TSV shield, signal attenuation from the lossy silicon substrate is eliminated, and unintentional signal coupling is avoided. In this paper, we propose and demonstrate a coaxial TSV 3D fabrication process. Next, the fabricated coaxial TSVs are characterized using s-parameters for high frequency analysis. The s-parameter data indicates the coaxial TSVs confine electromagnetic propagation by extracting the inductance and capacitance of the device. Lastly, we demonstrate the coaxial TSVs reduce signal attenuation and time delay by 35% and 25% respectively compared to the shield-less standard TSV technology. In addition, the coaxial interconnect significantly decreases electromagnetic coupling compared to traditional TSV architectures. The improved signal attenuation and high isolation of the coaxial TSV make it an excellent option for 3D packaging applications expanding into the millimeter wave regime.     

Long Retention of Gain-Cell Dynamic Random Access Memory With Undoped Memory Node

Low current leakage characteristics of a novel silicon-on-insulator (SOI) device are investigated in view of application to a gain-cell dynamic random access memory (DRAM). The device consists of a two-layered poly-Si gate. Since, in this device, the memory node is electrically formed by the gate in undoped SOI wire, no p-n junction is required. The retention is found to be dominated by the subthreshold leakage, which leads to long data retention. The device also achieved a fast (10 ns) writing time and its fabrication process is compatible with those of SOI MOSFETs. The present results, thus, strongly suggest a way of conducting a gain-cell DRAM to be embedded into logic circuits