双向移位寄存器在彩灯控制电路中双向递增控制的实现

双向移位寄存器74LS194是一种廉价的数字集成器件。本文介绍了双向移位寄存器的功能,设计并论述了由其控制的同向递增和反向递增两种彩灯控制电路,实现了对彩灯控制电路的双向递增控制,说明利用中规模集成电路可以实现结构简单、稳定可靠、经济适用的的彩灯控制电路。     

基于移位寄存器的伪随机序列改进算法

针对传统线性移位寄存器生成的伪随机序列输出数据速率低以及每个循环周期内0和1的数目不相等的问题,提出一种改进型的寄存器序列结构,采用跃进型移位寄存器为基础保证较高的输出速率,增加类似于De Bruijn计数器的反馈保证01平衡。理论分析与仿真结果表明,改进后的寄存器序列结构同时克服了原有结构的2个缺点,适合于高速率应用场合。     

双《原子模型》彩灯控制电路

本文叙述了双《原子模型》彩灯控制电路的工作原理及其设计方法。本电路巧妙地将环形计数器和约翰逊(Johnson)计数器结合于一体,并充分利用了两者的多种计数循环,定时地按一定时序自动进行转换,使彩灯灯光的旋转花样较多且新颖别致。运用本科研成果开发的技术完全可以制成“节日彩灯控制仪”用以控制剧场舞台、饭店酒楼、各种娱乐场所及各单位门楼外廓的节日彩灯。     

一种用GAL器件实现的可编程设计数器

介绍用一片GAL16V8实现的模≤2~n可编程计数器.它是基于“最大长度移位寄存器式计数器”的原理设计而成的,电路简单可靠,同时介绍一种由它组成的实用电路——由GAL实现时、分、秒计时的数字钟电路.     

基于FPGA的并串转换电路硬件实现

并串转换电路在通信接口中具有广泛的应用,可编程逻辑阵列由于具备灵活、可重构等特点非常适应于并串转换硬件电路的实现。为了解决硬件电路结构中资源与性能的矛盾,分析比较了移位寄存器、计数器与组合逻辑条件判定三种不同的并串转换硬件电路结构,并通过设计仿真对其进行了功能验证和性能评估。实验结果表明采用移位寄存器的实现方法具有最优的速度性能,采用计数器的实现方法具有最优的性价比,采用组合逻辑条件判定的实现方法具有最少的寄存器资源消耗,可根据实际应用需求合理选择并串转换硬件电路实现方式。     

PLC编程中理论与实际的差距

本人根据在教学过程中的实际应用,通过电动机的启动、停止、点动控制程序、计数器的应用程序、移位寄存器DATA端的使用编程等控制程序,浅议PLC编程中理论与实际的差距。     

基于FPGA的可变长度移位寄存器优化设计

结合FPGA的结构,针对高速数据采集系统中触发控制单元的特点,提出了采用优化结构的可变长度移位寄存器改进基于FPGA的触发控制单元的方法,同时从器件的搭配和寄存器结构两方面探讨了可变长度移位寄存器的优化方案,并给出了应用示例。     

一种低成本高性能开关量控制器的设计

本文给出了一种基于单片机和移位寄存器的低成本、高性能开关量控制器的设计。重点分析了采用移位寄存器构成多路开关量输入、输出通道时所特有的问题，并给出了相应用的解决措施。     

基于Multisim的八路彩灯控制系统的设计与仿真

Multisim是目前普遍使用的电子电路设计与仿真软件之一,是以Windows为基础的仿真工具,适用于板级的模拟/数字电路板的设计工作。本文以移位寄存器为核心,提出了一种基于Multisim的八路彩灯控制系统设计方法,通过了仿真分析,并在实际中得到了应用。     

晶体管—隧道二极管高速时序线路(下)

移位寄存器移位寄存器的作用就是,在接收到命令后把信息的位置同时移动一位或几位。它是一种用途很广的部件,比上述的计数器更为复杂。由于移位寄存器的工作要求几种功能的组合,并且其中每一种都可以用很多方法来实现,所以移位寄存器可能有很多种结构,每种都有不同的设计和工作特点。     

Modified dynamic current mode logic based LFSR for low power applications

Shift Register, which is a cascade of flip flops shares the same clock and the outputs are connected to the data input of the next one in the chain. Linear-feedback shift register or shortly LFSR is one such shift register whose input is a linear function of its previous state. Exclusive-OR (XOR) is the most commonly used linear function. LFSR's help in generating pseudo-random numbers, fast digital counters, pseudo-noise sequences and whitening sequences. LFSR's can be realised both using hardware and software. When it comes to hardware implementation, MOS current mode logic (MCML) method can be used for designing the LFSR. There are lots of drawbacks with the traditional MCML method including the static power dissipation, more power consumption at low frequencies as compared with CMOS circuits, inappropriate for large systems involving power-down modes and it's not a cost effective solution either. To overcome these issues and to achieve the high speed characteristics of MCML, we present the modified dynamic current mode logic and is a good solution for battery powered systems and portable solutions. Our simulation results also confirm the same where a 16 bit adder circuit fabricated using CMOS technology has only a delay of 1.22 ns and dissipates 19.0 mW at 400 MHz.     

Memory-based logic sequence generation

Simple methods of producing single or repetitive logic patterns entirely by RAM or PROM are described. These allow software loading and alteration of logic functions. It is shown that memories can emulate and, indeed, replace sequential logic circuits such as delay generators, binary counters, shift registers and multiple latches at frequencies in excess of 10 MHz. Examples of memory logic and free-running pattern generators are illustrated. Applications are suggested.     

An efficient signature computation method

A signature generation algorithm for linear-feedback shift register (LFSR)-based compactors used in fault simulation of built-in self-test digital circuits is presented. The algorithm uses small- to medium-size lookup tables to generate signatures for internal as well as external exclusive-OR LFSRs of any length. The basic concept can be extended to general linear compactors. Algorithms that convert signatures from one form of LFSR to the other are also presented     

采用计数器存储权值的人工神经网络的实现

文中提出了一种采用计数器存储权值的人工神经网络的实现方案。数字权值采用计数器存储,突触电路和神经元电路用模拟电路来实现。数字权值经脉冲宽度调制电路转换为脉冲信号作为模拟突触电路的输入信号。因而权值可以长期存储,对权值的修改易于实现,突触神经元电路结构简单,融合了人工神经网络模拟实现和数字实现的优点。对于智能计算机的实现具有重要的意义。     

Using a periodic square wave test signal to detect crosstalk faults

Built-in self test (BIST) scheme simplifies the detection of crosstalk faults in deep-submicron VLSI circuits in the boundary scan environment. The scheme tests for crosstalk faults with a periodic square wave test signal under applied random patterns generated by a linear feedback shift register (LFSR), which is transconfigured from the embedded circuit's boundary scan cells. The scheme simplifies test generation and test application while obviating the fault occurrence timing issue. Experimental results show that coverage for the induced-glitch type of crosstalk fault for large benchmark circuits can easily exceed 90%.     

Physical Register Reference Counting

Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and NoSQ (No Store Queue) rely on reference counting to manage physical registers. However, the register reference counting mechanism itself has received surprisingly little attention. This paper fills this gap by describing potential register reference counting schemes for NoSQ, CPR, and a hypothetical NoSQ/CPR hybrid. Although previously described in terms of binary counters, we find that reference counts are actually more naturally represented as matrices. Binary representations can be used as an optimization in specific situations.     

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel have been developed. The data drivers include shift registers, sample‐and‐hold circuits, and operational amplifiers, and drive LCD panels using a line‐at‐a‐time addressing method. To reduce the power consumption of the shift register, a dot‐clock control circuit has been developed. Using this circuit, the power consumption of the shift register has been reduced to 36% of that of conventional circuits. To cancel the offset voltage generated by the operational amplifier, an offset cancellation circuit for low‐temperature poly‐Si TFTs has been developed. This circuit is also able to avoid any unstable operation of the operational amplifier. Using this circuit, the offset voltage has been reduced to one‐third of the value without using the offset cancellation circuit. These data drivers have been connected to an LCD panel and have realized an SVGA display on a 12.1‐in. a‐Si TFT‐LCD panel.     

Provably good pattern generators for a random pattern test

This paper describes a pseudorandom pattern generator for the random pattern test of combinational circuits. Suppose that a fractionp of the possible patterns detects some fault and the generator generates L patterns to test the circuit. Then the probability that the generator generates a pattern that tests the fault is at leastpL/(pL + 1). The only assumption is that all values of the seed of the generator are equally likely. The seed is twice as long as a single pattern. The generator is less than twice as expensive as a linear feedback shift register. Thus, it can be used in practice. More complicated generators that achieve a better bound are also discussed.This research was supported in part by the National Science Foundation under Grants CCR-8810609 and CDA-8805910.     

可编程S盒及反馈移位寄存器的设计方法

可编程S盒和可编程反馈移位寄存器是可编程密码芯片的两个重要的部件。文章给出了可编程S盒和可编程反馈移位寄存器的一种逻辑设计方法,按照该方法设计的S盒能够通过编程实现任意的布尔逻辑函数,按照该方法设计的反馈移位寄存器能够通过编程灵活地改变反馈抽头和反馈函数。