Bandpass Delta Sigma A/D convertor using two-path multibit structure

The concept of an N-path bandpass Delta Sigma A/D convertor is introduced. A multibit sixth-order SC implementation is described. The new scheme appears to be very effective for the realisation of the narrowband bandpass delta-sigma modulators needed for communication applications.<>     

Nonlinearity correction for multibit /spl Delta//spl Sigma/ DACs

This paper presents a digital correction technique for wide-band multibit error-feedback (EF) digital-to-analog converters (DACs). The integral nonlinearity (INL) error of the multibit DAC is estimated (on line or off line) by a calibration analog-to-digital converter (CADC) and stored in a random-access memory table. The INL values are then used to compensate for the multibit DAC's distortion by a simple digital addition. The accuracy requirements for the error estimates are derived. These requirements can be significantly relaxed when the correction is combined with data-weighted averaging (DWA). Simulation and discrete-component measurement results are presented for a fourth-order 5-bit EF DAC. The results show a 14-bit DAC operating at an oversampling ratio of 8, which is suitable for digital subscriber line applications. The correction uses simple digital circuitry and a 3-bit CADC enhanced by DWA.     

All-digital gated ring oscillator $$\Delta \Sigma$$ modulators

This paper presents all-digital time-mode \(\Delta \Sigma\) modulators. The proposed modulators consist of a voltage-to-time integrator, a seven-stage gated ring oscillator functioning as a 3-bit quantizer, and seven digital differentiators. A detailed analysis of the nonlinear characteristics of the modulators is provided. Designed in IBM 130 nm 1.2 V CMOS technology with a 100 mV 100 kHz sinusoidal input and a 4.4 MHz frequency clock, the first-order modulator provides 47 dB SNR over 0–150 KHz bandwidth while consuming 1.1 mW while the second-order modulator provides 55 dB SNR over the same bandwidth while consuming consumes 1.45 mW.     

Experimental implementation of $$\Delta \Sigma $$AD modulator with dynamic analog components

This paper presents an experimental prototype of 2nd-order multi-bit \(\Delta \Sigma \)AD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feed-forward modulator is realized by a passive-adder embedded successive approximation register analog to digital converter which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a pre-amplifier is not used. Proposed modulator is fabricated in TSMC 90 nm CMOS technology. Measurement results of the modulator dynamic range is over 84 dB. Measured peak SNDR = 77.51 dB, SNR = 80.08 dB are achieved for the bandwidth of BW = 94 kHz while a sinusoid differential \(-1\) dBFS input is sampled at 12 MS/s. The total analog power consumption of the modulator is 0.37 mW while the supply voltage is 1.1 V.     

ΣΔ调制器的设计方法

介绍了sigma delta单环调制器的设计方法.详细阐述了如何把给定的要求转化为具体拓朴结构.通过该方法,设计者可以在仅知道精度要求的情况下,逐步实现所需要的电路结构,并通过-个三阶一位调制器的设计描述了这一流程.     

Design of low-voltage MOSFET-only /spl Sigma//spl Delta/ modulators in standard digital CMOS technology

A design strategy of low-voltage high-linearity MOSFET-only /spl Sigma//spl Delta/ modulators in standard digital CMOS technology is presented. The modulators use substrate-biased MOSFETs in the depletion region as capacitors, linearized by different compensation techniques. This work shows the design, simulation and measured results of a number of MOSFET-only /spl Sigma//spl Delta/ modulators using different implementations of so called compensated depletion-mode MOS capacitors. The modulators are designed for the demands of speech band applications. The performance of the modulators proves the capability of compensated depletion-mode MOS capacitors to fulfill analog circuit requirements at low supply voltages with reduced processing efforts.     

Continuous-time /spl Delta//spl Sigma/ modulators using distributed resonators

We derive a method for using distributed resonators in /spl Delta//spl Sigma/ modulators and demonstrate these /spl Delta//spl Sigma/ modulators have several advantages over existing /spl Delta//spl Sigma/ modulator architectures. Like continuous-time (CT) /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators do not require a high-precision track-and-hold, and additionally can take advantage of the high-Q of distributed resonators. Like discrete-time /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators are relatively insensitive to feedback loop delays and can subsample. We present simulations of several types of these /spl Delta//spl Sigma/ modulators and examine the challenges in their design.     

Hexagonal /spl Sigma//spl Delta/ modulators in power electronics

Design techniques for /spl Sigma//spl Delta/ modulators from communications are applied and adapted to improve the spectral characteristics of high frequency power electronic applications. A high frequency power electronic circuit can be regarded as a quantizer in an interpolative /spl Sigma//spl Delta/ modulator. We review one dimensional /spl Sigma//spl Delta/ modulators and then generalize to the hexagonal sigma-delta modulators that are appropriate to three-phase converters. A range of interpolative modulator designs from communications can then be generalized and applied to power electronic circuits. White noise spectral analysis of sigma-delta modulators is generalized and applied to analyze the designs so that the noise can be shaped to design requirements. Simulation results for an inverter show significant improvements in spectral performance.     

Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

This paper describes an architecture for stable high-order /spl Sigma//spl Delta/ modulation. The architecture is based on a hybrid /spl Sigma//spl Delta/ modulator, wherein hybrid integrators replace conventional analog integrators. The hybrid integrator, which is a combination of an analog integrator and a digital integrator, offers an increased dynamic range and helps make the resulting high-order /spl Sigma//spl Delta/ modulator stable. However, the hybrid /spl Sigma//spl Delta/ modulator relies on precise matching of analog and digital paths. In this paper, a calibration technique to alleviate possible mismatch between analog and digital paths is proposed. The calibration adaptively adjusts the digital integrators so that their transfer functions match the transfer functions of corresponding analog integrators. Through behavioral-level simulations of fourth-order /spl Sigma//spl Delta/ modulators, the calibration technique is verified.     

New class of multibit sigma-delta modulators using multiratearchitecture

A new multibit sigma-delta modulator is presented where the analogue-to-digital converter in the forward path is replaced by an increase in the clock rate of the integrators in the final stages. Theoretical and simulation results are presented for second- and third-order modulators     

Self-tuning algorithms for high-performance bandpass switched-capacitor /spl Sigma//spl Delta/ modulators

Switched-capacitor high-frequency bandpass /spl Sigma//spl Delta/ modulators could suffer from capacitor mismatch, finite opamp dc gain, and finite opamp bandwidth. These problems make the notch frequency and the quality factor of the zeros of the noise transfer function to deviate from their nominal values, strongly affecting the modulator dynamic range (DR). In order to avoid this situation, two sampled-data algorithms have been developed which allow to self-calibrate the bandpass /spl Sigma//spl Delta/ modulators. They use 3500 gate and 0.043 mm/sup 2/ area and consume power only when they are active, while, when the system is on, they are off and do not interfere with standard operation. The validity of the proposal is demonstrated by a silicon prototype in which the proposed solution allows to guarantee a 75-dB DR performance also under worst case conditions. In the particular case, it allows for the recovery of 3 dB in the SNR for the 200-kHz FM band (from 73 to 76 dB).     

Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays

An analytical design methodology for continuous-time (CT) bandpass (BP) /spl Sigma//spl Delta/ modulators is presented. Second- and fourth-order tunable continuous time BP /spl Sigma//spl Delta/ modulator design equations are presented. A novel /spl Sigma//spl Delta/ loop architecture, where the traditional CT BP loop filter function is replaced with the filter function with fractional delays, is proposed. Validity of the methodology is confirmed by mixed-signal behavioral simulations.     

低功耗Sigma Delta调制器的建模与设计

针对Sigma Delta ADC在实现高精度的同时如何降低系统功耗这一问题,通过进行建模分析,得出满足精度需求的最低性能指标。并对二阶Sigma Delta调制器的非理想因素进行数学建模分析,在满足ADC精度的同时对ADC组成模块的最低性能指标进行分配,利用SDtoolbox进行仿真验证。基于CSMC 0.5 μmCMOS工艺,在5 V电源电压下,对调制器进行了电路级设计。结果显示在模块最低性能时,调制器输出信号的带内信噪比为835 dB,总功耗为18 mW。     

Quadrature /spl Sigma//spl Delta/ modulators with a dynamic element matching scheme

This paper presents a new topology of a multibit quadrature bandpass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor implementations by using the same capacitors to sample the input and the reference of the feedback digital-analog converters (DACs). Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex bandpass case is proposed for the case of multibit feedback DACs.     

A fast block-based nonlinear decoding algorithm for /spl Sigma//spl Delta/ modulators

Previous work has established that the digital output of a /spl Sigma//spl Delta/ modulator as an A/D converter contains more information about the analog input than is extracted with conventional linear filtering. Under reasonable mathematical assumptions, optimal nonlinear decoding of the digital output can achieve significantly larger signal-to-noise ratios than linear filtering. However, the hitherto proposed decoding algorithms only demonstrate conceptual feasibility and are impractical from a computational point of view. We present a new block-based decoding algorithm that, like previous work, employs projections onto convex sets. The algorithm owes its speed to a change of projection norm, an accelerated convergence scheme, and a decimation-like subsampling; it is on the order of 10/sup 4/-10/sup 5/ times faster than one previously published algorithm for typical parameter values, and about 2-10 times slower than linear decoding. The new algorithm is applicable to all currently popular /spl Sigma//spl Delta/ architectures.<>     

A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass /spl Sigma//spl Delta/ modulator with on-chip switched buffer

A second-order multibit bandpass /spl Sigma//spl Delta/ modulator (BP/spl Sigma//spl Delta/M) used for the digitizing of AM/FM radio broadcasting signals at a 10.7-MHz IF is presented. The BP/spl Sigma//spl Delta/M is realized with switched-capacitor (SC) techniques and operates with a sampling frequency of 37.05 MHz. The input impulse current, required by the SC input branch, is minimized by the use of a switched buffer without deteriorating the overall system performance. The accuracy of the in-band noise shaping is ensured with two self-calibrating control systems. In a 0.18-/spl mu/m CMOS technology, the device die size is 1 mm/sup 2/ and the power consumption is 88 mW. In production, the BP/spl Sigma//spl Delta/M features at least 78-dB dynamic range and 72-dB peak SNR within a 200-kHz bandwidth (FM bandwidth). The intermodulation (IMD) is -65 dBc for two tones at -11 dBFS. The robustness of the aforementioned performance is demonstrated by the fact that it has been realized with the BP/spl Sigma//spl Delta/M embedded in the noisy on-chip environment of a complete mixed-signal FM receiver.     

Optimum selection of capacitive array for multibit Sigma-Delta modulators without DEM

A method for a smart selection and sequencing of unity capacitors in a multibit digital-to-analog converter (DAC) that improves the linearity is proposed. The approach, suitable for the DAC nonlinearity correction in Sigma-Delta modulators, obtains better results than dynamic element matching. The key of the proposed technique is an off-line self-measurement of mismatches with the available hardware. The results significantly improve when redundant DAC capacitors are introduced. Hence, the capacitors are selected from a set that is larger than required. An affordable silicon area overhead introduced by the redundant capacitors avoids extra power consumption, that is unavoidable in other methods during the normal operation of the converter.     

A vertically integrated tool for automated design of /spl Sigma//spl Delta/ modulators

We present a tool that starting from high-level specifications of switched-capacitor (SC) /spl Sigma//spl Delta/ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced /spl Sigma//spl Delta/ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order /spl Sigma//spl Delta/ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order /spl Sigma//spl Delta/ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 /spl mu/m CMOS double-metal double-poly technology.<>