A wireless multi-channel implantable neural recording microsystem based on optimized analog TDM-FDM combination

Crosstalk noise (CT) is a limiting factor to increase the number of channels in analog Time-Division-Multiplexing (TDM)-based Wireless Neural Recording microsystems (WNRs). This paper proposes a novel approach to mitigate and decrease the effect of the CT by combining TDM with Frequency-Division-Multiplexing (FDM). In particular, we evaluate some possible configurations of the TDM-FDM combination and present a system that has less CT than other configurations. A 12-channel WNR based on the proposed system is designed in both system and circuit-level. In this system, channels are first divided into three 4-channel groups and after multiplexing in time domain, they are combined together with FDM method. While the group containing the marker pulse is located in the base-band, the second and third group are shifted to the frequency domain by employing quadrature modulation. The circuit-level of the system is designed and simulated by using 0.18 μm CMOS technology. The designed circuit consumes a power of 1.4 mW at a supply voltage of 1.8 V. The performance of the proposed system is also compared with simple TDM-based WNR. Simulations shows that in the proposed system the CT is considerably decreased.     

基于FFT的OFDM-UWB系统的均衡接收

以双带OFDM-UWB通信系统为背景,分析了基于FFT算法的三种均衡接收方法-迫零均衡、MMSE均衡和相位均衡.在Matlab的simulink平台上对信道CM1进行仿真,结果表明:为了使系统误比特率达到10-4的性能,采用相位均衡方法需要的SNR最低,仅为2dB;可见,OFDM-UWB通信系统相位均衡接收方法的系统性能比其它均衡接收方法都要好.     

Combining frequency-division and code-division multiplexing in ahigh-capacity optical network

The combination of frequency division and code division multiplexing in a multiaccess network such that the beneficial aspects of each technique mitigate the shortcomings of the other is addressed. The feasibility and expected performance of the resulting hybrid network are examined. CDMA (code-division multiple access) is used to eliminate the need for laser frequency control, which is required for pure FDMA (frequency-division multiaccess) schemes. On the other hand, an FDMA-like mutual avoidance scheme exploits the limited tunability available to keep signals away from one another as much as possible, relieving the need for CDMA to protect against more than the occasional crossover of one interfering signal. This significantly limits the amount of spectral spreading required. The use of the hybrid network for high-bit-rate and low-bit-rate applications is discussed. The power budget for a local network utilizing a star coupler is outlined     

A low-noise clockless simultaneous 32-channel wireless neural recording system with adjustable resolution

We present a 32-channel wireless implantable neural recording (WINeR-5) system-on-a-chip (SoC) that operates based on time division multiplexing (TDM) of pulse width modulated (PWM) samples, similar to a single-slope analog to digital converter (ADC) that is made wireless. By transmitting a TDM–PWM signal, we have relaxed the need for wide bandwidth and accurate timing between transmitter and receiver units, which is necessary in wideband digital wireless links. The WINeR-5 system uses FSK modulation scheme with RF carrier at 898/926 MHz. The baseband TDM–PWM signal bandwidth is 18 MHz, which is also the bandwidth of the receiver baseband low-pass filter. Further, by moving the digitization circuitry outside the body, we have reduced the size, complexity, and power consumption of the implantable unit. A clockless asynchronous design has been utilized to manage TDM switching times such that no switching occurs during sensitive PWM onsets. Control over sampling rate, dynamic range, and resolution provides the user with tradeoffs that can optimize the system performance for the intended application. The SoC has been implemented in a 0.5-μm standard CMOS process, measuring 3.3 × 3 mm² and consuming 5.6 mW at ±1.5 V when all channels are active. Measured input referred noise for the entire system, including the receiver at 1 m distance, is 4.9 μV_rms in 1 Hz–8.8 kHz range. Functionality of the WINeR-5 system has also been demonstrated in acute in vivo experiments.     

A wireless implantable multichannel digital neural recording systemfor a micromachined sieve electrode

This paper reports the development of an implantable, fully integrated, multichannel peripheral neural recording system, which is powered and controlled using an RF telemetry link. The system allows recording of ±500 μV neural signals from axons regenerated through a micromachined silicon sieve electrode. These signals are amplified using on-chip 100 Hz to 3.1 kHz bandlimited amplifiers, multiplexed, and digitized with a low-power (<2 mW), moderate speed (8 μs/b) current-mode 8-b analog-to-digital converter (ADC). The digitized signal is transmitted to the outside world using a passive RF telemetry link. The circuit is implemented using a bipolar CMOS process. The signal processing CMOS circuitry dissipates only 10 mW of power from a 5-V supply while operating at 2 MHz and consumes 4×4 mm² of area. The overall circuit including the RF interface circuitry contains over 5000 transistors, dissipates 90 mW of power, and consumes 4×6 mm² of area     

Low-power high-sensitivity spike detectors for implantable VLSI neural recording microsystems

A spike detector has become a necessity of a contemporary multichannel neural recording microsystem for data-compression. This paper proposes two spike detection algorithms, frequency-enhanced nonlinear energy operator (fNEO) and energy-of-derivative (ED), to solve the sensitivity degradation suffered by the conventional nonlinear energy operator (NEO) at the presence of large-amplitude baseline interferences. The efficiency of NEO, fNEO and ED algorithms are evaluated with Simulink programs firstly and then implemented into three low-power spike detectors with a standard 0.13- \(\mu m\) CMOS process. To achieve a low-power design, subthreshold CMOS analog multipliers, derivatives and adders are developed to work with a low supply voltage, 0.5 V. The power dissipation of the proposed fNEO spike detector and ED spike detector are only 258.7 and 129.4 nW, respectively. The quantitative investigation shown in the paper indicates that both fNEO and ED spike detectors achieves superior performance than the conventional NEO spike detector. Considering its lowest power dissipation, the ED spike detector is selected for our application. Further statistical evaluations based on the true positive and false positive detection rate proves that the ED spike detectors achieves higher detection rate than that of the conventional NEO spike detector but dissipates 48 % less power.     

基于STM32的24路舵机同步控制系统设计

针对多路舵机速度和位置同步控制问题,提出一种多路舵机控制信号产生及控制方法,仅采用STM32芯片的一个通用定时器实现24路舵机PWM控制信号的精确独立输出控制。基于分时复用的方法,实现一个比较寄存器控制6路舵机,故利用一个定时器的4个比较寄存器及其比较中断和1个更新中断,最终实现24路舵机位置和速度的同步控制。基于该方法进行了硬件系统设计,主要包括电源模块、舵机接口模块、存储模块、低压报警模块、键盘模块及通信模块。最后,实现了24路舵机控制系统的设计,并成功应用在17自由度的人形机器人中,且在华北五省(市、自治区)大学生机器人大赛中获得一等奖,验证了控制系统的稳定性、可靠性及有效性。     

A 16-channel CMOS neural stimulating array

A probe designed for the highly selective long-term stimulation of neuronal assemblies in the central nervous system is described. The micromachined multishank probe incorporates CMOS circuitry to control the output current on 16 iridium oxide (IrO) electrode sites. Serial site addresses and current amplitude data are loaded into the probe at 4 MHz and converted to analog stimulus currents. The probe circuitry dissipates only 80 μW from ±5-V supplies when not delivering stimulus currents and uses five external leads. It permits the IrO sites to be activated by voltammetry from off-chip, provides per-channel pulse time-outs to prevent accidental overstimulation of the tissue, and signals the external world, using a status bit, in the event of certain trouble conditions. The stimulating site impedances and the stimulus currents can be measured from off chip on demand. The circuitry is implemented in a single-metal, single-poly, CMOS process with 3-μm minimum features using 7100 transistors in an area of 11 mm²     

Multichannel neural recording system based on family ASICs processed in submicron technology

In this paper we present a measurement system for in vivo multichannel recordings of the electrophysiological activity of brain tissue. The system consists of penetrating Microelectrode Array (MEA), three versions of a Conditioning Module each equipped with different Application Specific Integrated Circuits (ASIC), Digitizer and PC Application for recorded data presentation and storage. The MEA consists of 64 15 μm diameter microelectrodes. The multichannel ASICs amplify and filter field and action potential signals. The custom-made Digitizer Module simultaneously acquires data from all channels with a 14 kS/s sample rate and 12 bit resolution. The resulting byte stream (about 2 MB/s) is transmitted to the PC via USB (Universal Serial Bus). Eventually the measurement data is decoded, presented to the system user and stored on a HDD. Preliminary system tests confirm its excellent performance (low input refereed noise, low power consumption, low area occupancy, ability of Action Potentials/Local Field Potentials separation). Our system equipped with multichannel ASICs meets requirements of many different neurobiology experiments.     

Application of discontinuous communications in channels with random parameters to transmit narrowband signals and signals with orthogonal frequency-division multiplexing

An algorithm for increasing the interference immunity is analyzed in the case where the discontinuous communications method and its interconnecting with diversity reception in a Rayleigh channel are used for narrowband signals and signals with orthogonal frequency-division multiplexing. It is demonstrated that the probability of errors can be diminished without a significant decrease in spectral efficiency.     

Optical time division multiplexing: systems and networks

The recent advances in optical time division multiplexed (OTDM) systems and components research show the technique to be highly suited to the generation and transmission of high capacity data on a single optical carrier. This approach uses a single wavelength to carry capacities of at least 40 Gb/s. Such systems are based on a clock frequency and tributary data rates which are easily accessible using electronic components. Short optical pulses are used in a return-to-zero data transmission format with temporal interleaving to map a number of optical data channels into a single electronic clock cycle. It is an approach that can be used to achieve extremely high data-rate bit interleaved systems. This article summarizes the developments in this field and outlines a possible methodology to evolve transport networks to encompass the potential that both WDM and OTDM have to offer     

基于自适应空分复用的分组多用户分集方案

在采用空分复用技术的多用户多输入多输出下行链路中,有限的空域信道资源限制了系统容量.针对这一问题,提出了一种新的基于自适应空分复用的分组多用户分集方案.针对空分复用算法的特点,该方案首先以信道响应矩阵主右奇异向量的互相关大小为度量,将全部用户分为互相关最小的若干组;然后采用一种新的自适应空分复用算法,求出每一组用户传输时所能获得的系统容量,并将信道分配给容量最大的那一组用户.仿真结果表明,所提出的方案不仅能保证信道资源调度的公平性,而且通过引入多用户分集和自适应空域信道分配,显著地提升了系统容量.     

基于神经网络的实时故障诊断系统设计

本文以某型飞机电力起动系统为对象,介绍了如何将神经网络应用于飞机电力起动系统的故障诊断,较好地解决了利用故障字典法对该系统实施故障诊断时所存在的缺乏自组织、自学习能力和测试信号选取受限等弊端,建立了该系统的故障样本并对其进行了仿真研究。     

A low-power low-noise CMOS amplifier for neural recording applications

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.     

A micromachined silicon depth probe for multichannel neural recording

A process of making a new type of silicon depth-probe microelectrode array is described using a combination of plasma and wet etch. The plasma etch, which is done using a low temperature oxide (LTO) mask, enables probe thickness to be controlled over a range from 5 to 90 mu. Bending tests show that the probe's mechanical strength depends largely on shank thickness. More force can be applied to thicker shanks while thinner shanks are more flexible. One can then choose a thickness and corresponding mechanical strength using the process developed. The entire probe shaping process is performed only at low temperature, and thus is consistent with the standard CMOS fabrication. Using the probe in recording from rat's somatosensory cortex, we obtained four channel simultaneous recordings which showed clear independence among channels with a signal-to-noise ratio performance comparable with that obtained using other devices.     

Omega network-based ATM switch with neural network-controlledbypass queueing and multiplexing

Multistage interconnection networks (MINs) have long been studied for use in switching networks. Since they have a unique path between source and destination and the intermediate nodes of the paths are shared, internal blocking can cause very poor throughput. This paper proposes a high throughput ATM switch consisting of an Omega network with a new form of input queues called bypass queues. We also improve the switch throughput by partitioning the Input buffers into disjoint buffer sets and multiplexing several sets of nonblocking cells within a time slot, assuming that the routing switch operates only a couple of times faster than the transmission rate. A neural network model is presented as a controller for cell scheduling and multiplexing in the switch. Our simulation results under uniform traffic show that the proposed approach achieves almost 100% of potential switch throughput     

Three-dimensional photorefractive memory based on phase-code androtation multiplexing

This paper reviews the recent research in the development of three-dimensional optical memories based on phase-code and rotation multiplexing. The theory of phase-code multiplexing as well as rotation multiplexing is discussed. The construction of generalized Hadamard phase codes is presented that ensures the full utilization of the limited number of pixels of currently available spatial light modulators (SLMs). The preliminary experimental results are provided. A demonstration system with off-the-shelf devices is proposed     

Design of low cross-talk and high-quality-factor 2-channel and 4-channel optical demultiplexers based on photonic crystal nano-ring resonator

Photonic Network Communications - In this paper, 2-channel and 4-channel optical demultiplexers have been designed based on photonic crystal nano-ring resonator. The structure of both...