A wireless multi-channel implantable neural recording microsystem based on optimized analog TDM-FDM combination

Crosstalk noise (CT) is a limiting factor to increase the number of channels in analog Time-Division-Multiplexing (TDM)-based Wireless Neural Recording microsystems (WNRs). This paper proposes a novel approach to mitigate and decrease the effect of the CT by combining TDM with Frequency-Division-Multiplexing (FDM). In particular, we evaluate some possible configurations of the TDM-FDM combination and present a system that has less CT than other configurations. A 12-channel WNR based on the proposed system is designed in both system and circuit-level. In this system, channels are first divided into three 4-channel groups and after multiplexing in time domain, they are combined together with FDM method. While the group containing the marker pulse is located in the base-band, the second and third group are shifted to the frequency domain by employing quadrature modulation. The circuit-level of the system is designed and simulated by using 0.18 μm CMOS technology. The designed circuit consumes a power of 1.4 mW at a supply voltage of 1.8 V. The performance of the proposed system is also compared with simple TDM-based WNR. Simulations shows that in the proposed system the CT is considerably decreased.     

A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System

Recent work in field of neuroprosthetics has demonstrated that by observing the simultaneous activity of many neurons in specific regions of the brain, it is possible to produce control signals that allow animals or humans to drive cursors or prosthetic limbs directly through thoughts. As neuroprosthetic devices transition from experimental to clinical use, there is a need for fully-implantable amplification and telemetry electronics in close proximity to the recording sites. To address these needs, we developed a prototype integrated circuit for wireless neural recording from a 100-channel microelectrode array. The design of both the system-level architecture and the individual circuits were driven by severe power constraints for small implantable devices; chronically heating tissue by only a few degrees Celsius leads to cell death. Due to the high data rate produced by 100 neural signals, the system must perform data reduction as well. We use a combination of a low-power ADC and an array of "spike detectors" to reduce the transmitted data rate while preserving critical information. The complete system receives power and commands (at 6.5 kb/s) wirelessly over a 2.64-MHz inductive link and transmits neural data back at a data rate of 330 kb/s using a fully-integrated 433-MHz FSK transmitter. The 4.7times5.9 mm² chip was fabricated in a 0.5-mum 3M2P CMOS process and consumes 13.5 mW of power. While cross-chip interference limits performance in single-chip operation, a two-chip system was used to record neural signals from a Utah Electrode Array in cat cortex and transmit the digitized signals wirelessly to a receiver     

Design and electrochemical measurement of a current-mode analog-to-time converter with short-pulse output capability using local intra-cell activation for high-speed time-domain biosensor array

Functional electrical stimulation has been widely used for the restoration of bladder functions after spinal cord injury or other neurological disorders. However, most of the neuroprostheses for bladder control are still imperfect due to lack of the feedback information about the state of the controlled bladder. The purpose of this study is to develop an implantable system which allows us to stimulate the nerves and record the nerve signals related to the condition of the bladder. The proposed stimulator consists of three parts: a digital-to-analog converter (DAC), a current driver, and a switch network. Using the same current source with a switch network eliminates the need for separate current sources for anodic and cathodic sections and reduce the need for interconnect lines of control signals which is an area-saved and power-efficient configuration. A symmetrical regulated cascode current driver is used to implement a high voltage compliance and a high output impedance which improves its ability with load. The amplitude, frequency and the pulse width of the stimulating current are adjusted by encoding the DAC and switch sequences, respectively. In addition, we also present two-stage fully differential capacitively-coupled amplifiers for neural recording. The neural amplifier’s parameters are carefully chosen according to the characteristics of neural signal; meanwhile, we analyzed theoretically the main noise sources, especially the pseudo-resistor in the feedback path which gives little attention by previous studies. The integrated neural stimulating and recording frontend for bladder control prosthesis has been designed and simulated, using a TSMC’s 0.18-μm CMOS process. The proposed stimulator can provide a symmetrical cathodic-first biphasic current pulse with interphasic gap, a low headroom voltage of 0.168 V corresponding to 2.48 mA full-scale current, an adjustable pulse width of 100–500 μs and frequency of 1–40 Hz. The recording amplifier with a low input-referred noise of 3.62 μV, an NEF of 3.88 and a low power dissipation of 7.2 μW has a gain of 61.6 dB and a frequency bandwidth from 300 Hz to 5.3 kHz. Both circuit analysis and simulations are presented to examine the performance of the proposed designs.     

A low-noise clockless simultaneous 32-channel wireless neural recording system with adjustable resolution

We present a 32-channel wireless implantable neural recording (WINeR-5) system-on-a-chip (SoC) that operates based on time division multiplexing (TDM) of pulse width modulated (PWM) samples, similar to a single-slope analog to digital converter (ADC) that is made wireless. By transmitting a TDM–PWM signal, we have relaxed the need for wide bandwidth and accurate timing between transmitter and receiver units, which is necessary in wideband digital wireless links. The WINeR-5 system uses FSK modulation scheme with RF carrier at 898/926 MHz. The baseband TDM–PWM signal bandwidth is 18 MHz, which is also the bandwidth of the receiver baseband low-pass filter. Further, by moving the digitization circuitry outside the body, we have reduced the size, complexity, and power consumption of the implantable unit. A clockless asynchronous design has been utilized to manage TDM switching times such that no switching occurs during sensitive PWM onsets. Control over sampling rate, dynamic range, and resolution provides the user with tradeoffs that can optimize the system performance for the intended application. The SoC has been implemented in a 0.5-μm standard CMOS process, measuring 3.3 × 3 mm² and consuming 5.6 mW at ±1.5 V when all channels are active. Measured input referred noise for the entire system, including the receiver at 1 m distance, is 4.9 μV_rms in 1 Hz–8.8 kHz range. Functionality of the WINeR-5 system has also been demonstrated in acute in vivo experiments.     

Development of a TDM/FDM Transmultiplexer

Recently, digital systems such as digital telephone switching systems and digital transmission paths are being introduced more and more into communications networks in which signals are handled with Time Division Multiplex (TDM). There still exists, on the other hand, a number of analog transmission paths in which signals are multiplexed with Frequency Division Multiplex (FDM). Therefore, it is important to develop a scheme to interconnect efficiently TDM and FDM systems. Transmultiplexer, which is an equipment directly converting PCM.TDM signals and SSB.FDM signals with each other, is expected to provide an efficient interconneetion between TDM and FDM systems. Authors have developed an experimental transmultiplexer which can provide mutual conversion between a 24-channel PCM primary group (1.544 Mbits/s) and two 12-channel FDM basic groups (60-108 kHz). The developed equipment is designed so as to achieve reduction of the computation rate and simplicity of the hardware by the following techniques: (1) The FFT (Fast Fourier Transform) technique is used to optimize the filtering and multiplexing processes. (2) The spectrum reversion of odd-numbered channel signals is achieved by inverting the sign bits of the PCM signals every other frame. (3) The bandpass sampling technique is applied to obtain SSB.FDM signals directly without frequency shifts at analog FDM stages. In order to evaluate the characteristics of the developed transmultiplexer, experiments have been conducted by connecting it with FDM terminal equipments. The experimental results showed that the transmultiplexer can offer better performance than the tandem connection of standard PCM multiplex equipments and standard FDM terminal equipments with reasonable hardware.     

Microelectrodes, Microelectronics, and Implantable Neural Microsystems

Lithographically defined microelectrode arrays now permit high-density recording and stimulation in the brain and are facilitating new insights into the organization and function of the central nervous system. They will soon allow more detailed mapping of neural structures than has ever before been possible, and capabilities for highly localized drug-delivery are being added for treating disorders such as severe epilepsy. For chronic neuroscience and neuroprosthesis applications, the arrays are being used in implantable microsystems that provide embedded signal processing and wireless data transmission to the outside world. A 64-channel microsystem amplifies the neural signals by 60 dB with a user-programmable bandwidth and an input-referred noise level of 8 muV_rms before processing the signals digitally. The channels can be scanned at a rate of 62.5 kS/s, and signals above a user-specified biphasic threshold are transmitted wirelessly to the external world at 2 Mbps. Individual channels can also be digitized and viewed externally at high resolution to examine spike waveforms. The microsystem dissipates 14.14 mW from 1.8 V and measures 1.4 1.55 cm².     

A wireless implantable multichannel digital neural recording systemfor a micromachined sieve electrode

This paper reports the development of an implantable, fully integrated, multichannel peripheral neural recording system, which is powered and controlled using an RF telemetry link. The system allows recording of ±500 μV neural signals from axons regenerated through a micromachined silicon sieve electrode. These signals are amplified using on-chip 100 Hz to 3.1 kHz bandlimited amplifiers, multiplexed, and digitized with a low-power (<2 mW), moderate speed (8 μs/b) current-mode 8-b analog-to-digital converter (ADC). The digitized signal is transmitted to the outside world using a passive RF telemetry link. The circuit is implemented using a bipolar CMOS process. The signal processing CMOS circuitry dissipates only 10 mW of power from a 5-V supply while operating at 2 MHz and consumes 4×4 mm² of area. The overall circuit including the RF interface circuitry contains over 5000 transistors, dissipates 90 mW of power, and consumes 4×6 mm² of area     

A 0.7 V 6.66–9.36 GHz wide tuning range CMOS LC VCO with small chip size

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is ?110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about ?1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about ?180.7 and ?191.25 dBc/Hz, respectively. The chip area is 0.429 mm² excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.     

基于SOI硅片的硅微电极制作与评估

采用微机电系统(MEMS)工艺方法制作了基于SOI衬底的七通道硅微电极,用于视神经视觉修复.通过噪声分析确定了硅微电极的金属暴露位点的几何尺寸.优化设计了硅微电极的几何结构,以便于减小植入损伤.阻抗测试结果表明,当测试电压为50mVpp时,1kHz频率下,微电极的单通道阻抗为2.3MQ,适用于神经电信号记录.在体实验结果表明,动物初级视皮层记录到的神经电信号幅度为8μV.     

Micropower fully integrated CMOS readout interface for neural recording application

In this paper, we presented a micropower, small-size fully integrated CMOS readout interface for neural recording system. A crucial and important module of this system is the amplifier circuit with low-power low-noise. We describe a micropower low-noise readout circuit using an active feedback fully differential structure to reject the 1/f noise and large DC-offsets, the substrate-bias technology to further decrease the noise and power of the neural recording amplifier. Therefore, the neural amplifier with micropower low-noise and high input impedance is presented. The readout interface core, fully differential amplifier is implemented in 0.35-μm CMOS process, passes neural signals from 10 Hz to 9 kHz with an input-referred noise of 4.3 μV_rms. The power consumption of single amplifier is 5.6 μW while consuming 0.03 mm² of die area. The low cutoff frequencies of the circuit can adjusted from 10 Hz to 400 Hz, and the high cutoff frequencies form 4 kHz to 9 kHz.     

Calculation of dispersion and nonlinear effect limited maximum TDMand FDM bit rates of transform-limited pulses in single-mode opticalfibers

The dispersion-limited maximum time-division-multiplexed (TDM) bit rates and the optical nonlinear-effect-limited maximum frequency-division multiplexed (FDM) channel numbers in single-mode optical fibers have been calculated for transform-limited optical pulses. The total bit rate attainable with combinations of TDM and FDM on Gaussian-type transform-limited pulses is about 7 Tbt/s in the typical 15 THz wide low-loss region of single-mode fibers at each of 1.3 and 1.5 μm wavelength bands. The maximum total bit rate attainable with dispersion-shifted (DS) fibers in the Er-doped fiber amplifier (EDFA's) gain region of 1525-1565 nm is calculated to be about 2.3 Tbt/s, but reduces to 1.2 to 1.8 Tbt/s depending on fiber length for cases of a uniform TDM bit rate over the entire FDM channels. For DS fibers the four-wave mixing effect is a dominant effect limiting the channel power and the maximum FDM channel number, but for normal single-mode fibers the chromatic dispersion effect and cross-phase modulation (CPM) and stimulated Raman scattering (SRS) effects are dominant effects limiting the TDM bit rate and channel power, respectively     

A novel data transfer technique for bio-implantable devices through the inductive power transfer link

A novel technique for transferring data to biomedical implantable devices through the inductive power transfer link is presented. The new modulation technique presented in this paper is based on changing the duty cycle of the switching pulse of the class E power amplifier which drives the external coil. Hence, we call it duty cycle shift keying (DCSK). Inductive link efficiency and voltage gain are analyzed for the DCSK technique. Based on the mathematical analysis of the proposed technique its bit error rate is close to that of the BFSK. However, it can achieve a data rate to carrier frequency of 100 %. The modulator and demodulator of the proposed technique are simple and make it suitable for bio-implantable devices. The proposed circuit is simulated by advanced design system simulator using the 0.18 μm CMOS technology. Moreover, in order to verify the effectiveness of the proposed technique, a test setup is implemented using off-the-shelf components. The simulation as well as measurement results will be provided in this article.     

On the reduction of thermal and flicker noise in ENG signal recording amplifiers

Because of the extremely low amplitude of the input signal, the design of electro-neuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable electronics, because power consumption is restricted to few hundreds μW. In this work, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable medical devices, are demonstrated. The circuit design, and measurement results are presented, in both cases showing an excellent performance, and noise to power consumption trade-off. In the first circuit, a very simple low-pass G_m–C chopper amplifier is used for flicker noise cancellation. It consumes only 28 mW, with a measured input referred noise and offset of 2  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ , and 2.5 μV, respectively. In the second circuit, a ultra-low noise amplifier, a energy-efficient DC–DC down-converter, and low voltage design techniques are combined, for the reduction of thermal noise with a minimum power consumption. Measured input referred noise in this case was 5.5  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ at only 380 μW power consumption. Both circuits were fabricated in a 1.5 μm technology.     

A 2 MHz Wireless CMOS Transceiver for Implantable Biosignal Sensing Systems

An implementation of an implantable sensing biosystem composes of a readout circuit, a power management block, an embedded microcontroller unit (MCU), an implantable drug delivery section and a wireless uplink transceiver system. This paper describes a bi-directional wireless transceiver system for implantable sensing systems. The transceiver system is composed of an external and implantable transceiver, communicating through an inductive link. Half duplex communication between transceivers at a 10 Kbps data rate was achieved at a maximum distance of 4 cm. Command and data will be supplied to the implantable module by radio frequency (RF) telemetry utilizing an amplitude shift keying (ASK) modulated 2 MHz carrier frequency. A capacitor-less amplitude demodulation receiver architecture was produced in the research with implantable receiver core area measuring at 113.2 μm by 171.8 μm with average power dissipation at 815.1 μW at a 3.3 V single rail power supply. An active uplink transceiver utilizing load shift keying (LSK) as backward data telemetry was designed. Implantable transmitter core area measures 251.7 μm by 139.3 μm, consuming 103.62 mW while driving an RF ferrite core antenna at maximum reading range. Integrating both circuits, implantable transceiver, measuring 355.3 μm by 171.8 μm, was designed and implemented using TSMC 0.35 μm mixed-signal 2P4M 3.3 V standard CMOS process. The integrated circuit solution addressed solutions for many of the problems associated with implanted devices and introduces circuits which improve in several ways over previously published designs, in functionality and integration level. In addition to being fully integrated in plain CMOS technology, not relying at least partly on available specialized elements and expensive technologies, these building blocks improve on previous designs in performance and/or power consumption. This work succeeded in implementing building blocks for an implantable transceiver, which depends only on the absolute minimum off-chip components. A complete implantable chip is presented, which highlight the design tradeoffs and optimizations applied to the design of CMOS implantable system chips.     

MEASUREMENTS OF THE TIME STATISTICS OF FMTV SPECTRA AND TV INTERFERENCE INTO FDM/FM CARRIERS

When computing the amount of interference from FMTV signals in satellite systems, it is customary to consider that the only effective TV modulation is the energy dispersal signal (EDS). This leads to a sufficient but highly conservative system design, since for most of the time the wanted demodulated signal may experience interference levels well below that computed using this approach. If the time statistics of the interference can be determined through measurement, then a grade-of-service approach can be taken in which interference can be guaranteed not to exceed a certain level for more than a prescribed fraction of the time. This approach will lead to more efficient use of orbit/spectrum resources as a result of the implementation of less conservative system designs. This paper presents a simulation approach used to ‘measure’ FMTV power spectra with and without EDS and the corresponding interference powers into the basebands of FDM/FM carriers. Time statistics in the form of FMTV spectral masks and FDM baseband interference power time distributions have been derived from the measured data of 1000 off-air TV frames for co-channel TV and standard FDM/FM carrier sets (12 to 1200 channels) deployed by INTELSAT. Sample results are given.     

Integrated control circuit for adaptive sampling

A fully integrated controller for non-uniform data sampling suitable for the pre-processing of signals in a power- and size-restricted sensor front-end is presented. The sample rate is dynamically varied based on signal activity determined by the 2nd derivative of the input voltage. The derivative is realized with high-pass filters having 647 Hz cut-off frequency. A digital circuit generates the time-stamps and the trigger for an external analog-to-digital converter. Measured results of a 0.35 μm CMOS implementation show a sample rate variation of 7:1 and a system power advantage compared to conventional front-ends. The circuit dissipates 48 μW from ±1.5 V supplies and consumes an active area of 0.068 mm².     

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-μm CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of ?47.2 dBm while consuming only 6.8 μW from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.     

Design Optimization for Integrated Neural Recording Systems

Power and chip area are the most important parameters in designing a neural recording system in vivo. This paper reports a design methodology for an optimized integrated neural recording system. Electrode noise is considered in determining the ADC's resolution to prevent over-design of the ADC, which leads to unnecessary power consumption and chip area. The optimal transconductance and gain of the pre-amplifiers, which minimizes the power–area product of the amplifier, are mathematically derived. A numerical example using actual circuit parameters is shown to demonstrate the design methodology. A tradeoff between the power consumption of the system and the chip area in terms of the multiplexing ratio is investigated and the optimal number of channels per ADC is selected to achieve the minimum power–area product for the entire system. Following the proposed design methodology, a chip has been designed in 0.35 $mu{hbox{m}}$ CMOS process, with the multiplexing ratio of 16:1, resulting in total chip area of 2.5 mm $times$ 2.0 mm and power consumption of 5.3 mW from $pm$1.65 V.      

Wireless monitoring of electrode-tissues interfaces for long term characterization

The electrode-tissues interface (ETI) is one of the key issues for the safety, reliability and efficiency of implantable devices such as stimulators and sensors. The aim of this paper is to report an integrated circuit (IC) that was designed as part of an implantable telemetry device to monitor the ETI. The proposed system performs various types of measurements, such as impedance spectroscopy, cyclic voltammetry, and galvanostatic double pulse method. Hence, the evolution of various electrochemical parameters of the ETI such as complex impedance, faradic resistance, double layer capacity, rheobase current, and chronaxy time, could be monitored long time after implantation. Deviation from nominal impedance for example could indicate electrodes faults as well as nerve conduction changes. The full custom IC has been designed and fabricated with the CMOS 0.18 μm technology. The circuit occupies a silicon area of 2 mm², and consumes less than 3 mW during measurements. Characterisation and in-vivo experimental results validate the full functionalities of the implantable monitoring system including the custom IC.     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.