Monitoring the De-Inking Process through Neural Network-Based Colour Image Analysis

This paper presents an approach to determining the colours of specks in an image of a pulp being recycled. The task is solved through colour classification by an artificial neural network. The network is trained using fuzzy possibilistic target values. The number of colour classes found in the images is determined through the self-organising process in the two-dimensional self-organising map. The experiments performed have shown that the colour classification results correspond well with human perception of the colours of the specks.     

Medical image compression using topology-preserving neural networks

A novel method based on topology-preserving neural networks is used to implement vector quantization for medical image compression. The described method is an innovative image compression procedure, which differentiates itself from known systems in several ways. It can be applied to larger image blocks and represents better probability distribution estimation methods. A transformation-based operation is applied as part of the encoder on the block-decomposed image. The quantization process is performed by a “neural-gas” network which applied to vector quantization converges quickly to low distortion errors and reaches a distortion error lower than that resulting from Kohonen's feature map or the LBG algorithm. To study the efficiency of our algorithm, we blended mathematical phantom features into clinically proved cancer free mammograms. The influence of the neural compression method on the phantom features and the mammo-graphic image is not visually perceptible up to a high compression rate.     

VLSI Implementation of Discrete Wavelet Transform for Lossless Compression of Medical Images

This paper presents a VLSI architecture to implement the forward and inverse two dimensional Discrete Wavelet Transform (DWT), to compress medical images for storage and retrieval. Lossless compression is usually required in the medical image field. The word length required for lossless compression makes too expensive the area cost of the architectures that appear in the literature. Thus, there is a clear need for designing a cost-effective architecture to implement the lossless compression of medical images using DWT. The data path word length has been selected to ensure the lossless accuracy criteria leading a high speed implementation with small chip area. The pyramid algorithm is reorganized and the algorithm locality is improved in order to obtain an efficient hardware implementation. The result is a pipelined architecture that supports single chip implementation in VLSI technology. The implementation employs only one multiplier and 352 memory elements to compute all scales what results in a considerable smaller chip area (45 mm²) than former implementations. The hardware design has been captured by means of the VHDL language and simulated on data taken from random images. Implemented in a 0.7 μm technology, it can compute both the forward and inverse DWT at a rate of 3.5 512×512 12 bit images/s corresponding to a clock speed of 33 MHz. This chip is the core of a PCI board that will speedup the DWT computation on desktop computers.     

Full-frame cosine transform image compression for medical and industrial applications

Full-frame image compression capable of a 101 ratio or higher was developed for radiological applications where block artifacts are not acceptable. Applications in machine vision with similar stringencies can utilize the same principles and hardware design. Subsecond compression speed for image sizes up to 1K × 1K × 8 can be achieved by DMA and DSP designs using off-the-shelf components and customized bus architecture. Successions of completed hardware module design and proposed enhancements are reported with technical details. The possibility of 512 × 512 × 8 image compression in real time is also explored with design examples.     

A pipelined array architecture for Euclidean distance transformation and its FPGA implementation

The Euclidean Distance Transform (EDT) is an important tool in image analysis and machine vision. This paper provides an area-efficient hardware solution to the computation of EDT on a binary image. An O(n) hardware algorithm for computing EDT of an n×n image is presented. A pipelined 2D array architecture for harware implementation is designed. The architecture has a regular structure with locally connected identical processing elements. Further, pipelining reduces hardware resources. Such an array architecture is easily scalable to handle images of different sizes and is suitable for implementation on reconfigurable devices like FPGAs. Results of FPGA-based implementation shows that the hardware can process about 6000 images of size 512×512 per second which is much higher than the video rate of 30 frames per second.     

A novel hardware-oriented Kohonen SOM image compression algorithm and its FPGA implementation

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The major drawback of the software implementation of this technique is its very computational intensive task. Fortunately, the structure is fairly easy to convert into hardware processing units executing in parallel. The resulting hardware system, however, consumes much of a microchip’s internal resources, i.e. slice registers and look-up table units. This results in utilising more than a single microchip to realize the structure in pure hardware implementation. Previously proposed K-SOM realizations were mainly targetted on implementing on an application specific integrated circuit (ASIC) with low restriction on resource utilization. In this paper, we propose an alternative architecture of K-SOM suitable for moderate density FPGAs with acceptable image quality and frame rate. In addition, its hardware architecture and synthesis results are presented. The proposed K-SOM algorithm compromises between the image quality, the frame rate throughput, the FPGA’s resource utilization and, additionally, the topological relationship among neural cells within the network. The architecture has been proved to be successfully synthesized on a single moderate resource FPGA with acceptable image quality and frame rate.     

多尺度显著区域检测图像压缩

目的 为了解决利用显著区域进行图像压缩已有方法中存在的对多目标的图像内容不能有效感知,从而影响重建图像的质量问题,提出一种基于多尺度深度特征显著区域检测图像压缩方法。方法 利用改进的卷积神经网络（CNNs）,进行多尺度图像深度特征检测,得到不同尺度显著区域;然后根据输入图像尺寸自适应调整显著区域图的尺寸,同时引入高斯函数,对显著区域进行滤波,得到多尺度融合显著区域;最后结合编码压缩技术,对显著区域实行近无损压缩,非显著区域利用有损编码技术进行有损压缩,完成图像的压缩和重建工作。结果 提出的图像压缩方法较JPEG压缩方法,编码码率为0.39 bit/像素左右时,在数据集Kodak PhotoCD上,峰值信噪比（PSNR）提高了2.23 dB,结构相似性（SSIM）提高了0.024;在数据集Pascal Voc上,PSNR和SSIM两个指标分别提高了1.63 dB和0.039。同时,将提出的多尺度特征显著区域方法结合多级树集合分裂（SPIHT）和游程编码（RLE）压缩技术,在Kodak数据集上,PSNR分别提高了1.85 dB、1.98 dB,SSIM分别提高了0.006、0.023。结论 提出的利用多尺度深度特征进行图像压缩方法得到了较传统编码技术更好的结果,该方法通过有效地进行图像内容的感知,使得在图像压缩过程中,减少了图像内容损失,从而提高了压缩后重建图像的质量。     

一种利用回归神经网络黑白图像着色算法研究

研究了利用神经网络对序列黑白(灰度)图像进行着色的问题。针对以往基于人工或者半自动化技术的黑白图像着色技术效率低下、视觉效果较差的缺陷,提出了一种利用三层神经网络、无须人工干预的图像自动着色算法。首先将灰度图像分割成小块,通过对小块提取灰度特征、空间特征等作为神经网络的输入,训练得到一个回归神经网络。在着色过程中,可以利用该神经网络将图像中各像素由灰度空间投影到一个经过压缩的色彩空间,从而实现了图像的自动着色过程。实验结果显示本方法能有效地将灰度图像着色,并且由于使用了一个压缩的色彩空间,使得计算效率和着色效果都得到了有效的提高,能很好地逼近原始的真实图像。     

基于自组织特征映射神经网络的图像压缩

简要介绍了基于自组织特征映射(SOFM)神经网络的图像压缩的传统算法。通过对传统方法的优缺点分析，提出了一种新的简单的矢量量化压缩方法。新算法采用分类码书设计和残留编码，大大提高了图像的客观指标和主观视觉效果。实验表明此方法明显优于传统的SOFM算法，而且易于硬件实现。     

Haar wavelet based processor scheme for image coding with low circuit complexity

A hardware-oriented image coding processing scheme based on the Haar wavelet transform is presented. The procedure computes a variant of the Haar wavelet transform that uses only addition and subtraction operations, after that, an optimized methodology performs the selection and coding of the coefficients, tailored for it with the main aim of attaining the lowest circuit complexity hardware implementation. A selection strategy, which does not require the previous ordering of coefficients, has been used. A non-conventional coding methodology, which uses an optimized combination of techniques adapted to the various groups of coefficients, has been devised for the coding of the selected coefficients leading to a compressed representation of the image and reducing the coding problems inherent in threshold selection. The compression level reached for images of 512 × 512 pixels with 256 grey levels is just over 22:1, (0.4 bits/pixel) with a normalized mean square error, nrmse, of 2-3%, with subjective qualities which can be classified as good. The whole compression circuitry has been described and simulated at HDL level for up to 4 consecutive images, obtaining consistent results. The complete processor (excluding memory) for images of 256 × 256 pixels has been implemented using only one general-purpose low-cost FPGA chip, thus proving the design reliability and its relative simplicity.     

基于DSP的脱机远程视频监控终端

介绍一个基于DSP的脱机远程视频监控终端的设计和实现，该系统采用CPLD完成图像采集的控制逻辑，以ADSP-21535为中央处理器完成图像MPEG4编码、编码数据网络传输平和本地存储。介绍监控终端的系统结构与流程，以及图像采集模块和网络接口模块的软硬件设计与实现，给出了系统的性能指标。     

一种基于PCA/SOFM混合神经网络的图象压缩算法

鉴于用神经网络实现图象压缩是一种非常有效的方法,为此提出了一种基于PCA/SOFM混合神经网络的图象压缩编码算法,并对SOFM网络学习参数的优化进行了探讨.实验证明,与PCA SOFM连续编码算法和基本SOFM算法相比,这种混合编码算法,由于占用存储空间少,因而降低了码书设计的计算量,并改善了码书的性能.     

Selecting colour codes for a computer-generated topographic map based on perception experiments and functional requirements

Abstract

This paper describes a series of human factors analyses that guided the selection of chromaticities and luminances for a computer-generated topographic map. By virtue of its impressive computational capabilities, this CRT-displayed digital map will greatly facilitate the navigational accuracy and situational awareness of army helicopter aviators during low level and nap-of-the-earth flight. Colour codes were assigned to the digital map's point, linear and area features according to guidelines derived from four colour naming and two symbol search experiments. The design of each study was structured around the map's functional requirements: the five linear feature colours should have high luminance and support absolute colour identification; the three point symbol colours should be identifiable at small sizes; and the four area colours should minimize colour distortions, with the two terrain colours luminance-shaded to depict elevation information. Within these constraints, the results of the colour naming studies yielded an initial set of map colour codes by identifying the most frequently occurring colour confusions arising from the perceptual distortions of brightness contrast, colour contrast and Gaussian spread. The symbol search studies further refined colour selection by identifying the specific foreground/background colour combinations that hinder search, and by quantifying the conditions under which a colour or monochrome map facilitates symbol search.     

Example-Based Colourization Via Dense Encoding Pyramids

We propose a novel deep example-based image colourization method called dense encoding pyramid network. In our study, we define the colourization as a multinomial classification problem. Given a greyscale image and a reference image, the proposed network leverages large-scale data and then predicts colours by analysing the colour distribution of the reference image. We design the network as a pyramid structure in order to exploit the inherent multi-scale, pyramidal hierarchy of colour representations. Between two adjacent levels, we propose a hierarchical decoder–encoder filter to pass the colour distributions from the lower level to higher level in order to take both semantic information and fine details into account during the colourization process. Within the network, a novel parallel residual dense block is proposed to effectively extract the local–global context of the colour representations by widening the network. Several experiments, as well as a user study, are conducted to evaluate the performance of our network against state-of-the-art colourization methods. Experimental results show that our network is able to generate colourful, semantically correct and visually pleasant colour images. In addition, unlike fully automatic colourization that produces fixed colour images, the reference image of our network is flexible; both natural images and simple colour palettes can be used to guide the colourization.     

Weighted centroid neural network for edge preserving imagecompression

An edge preserving image compression algorithm based on an unsupervised competitive neural network is proposed. The proposed neural network, the called weighted centroid neural network (WCNN), utilizes the characteristics of image blocks from edge areas. The mean/residual vector quantization (M/RVQ) scheme is utilized in this proposed approach as the framework of the proposed algorithm. The edge strength of image block data is utilized as a tool to allocate the proper code vectors in the proposed WCNN. The WCNN successfully allocates more code vectors to the image block data from edge area while it allocates less code vectors to the image black data from shade or non-edge area when compared to conventional neural networks based on VQ algorithm. As a result, a simple application of WCNN to an image compression problem gives improved edge characteristics in reconstructed images over conventional neural network based on VQ algorithms such as self-organizing map (SOM) and adaptive SOM.     

Efficient parallel architecture for multi-level forward discrete wavelet transform processors

A resource efficient and high-performance architecture for a two-dimensional multi-level discrete wavelet transform processor is presented in this paper. The JPEG2000 standard integer lossless 5-3 filter has been implemented. It achieves optimal hardware utilisation with minimal combinational logic block slices and high frequency of operation. To reduce the hardware complexity and to achieve high performance the proposed architecture implements lifting scheme with a single multiplier-free processing element to perform both predict and update operations. Symmetric extension is used at image boundaries without requiring any extra clock cycle. The generic architecture is very flexible and can perform up to five levels of forward transform on any arbitrary image size. Synthesis of the 5-level architecture on Xilinx Virtex 5 FPGA shows that the processor can achieve a maximum frequency of operation of 221.44 MHz. The reduced hardware complexity and high frequency of operation render the design suitable for incorporation in image processing applications requiring fast operations. The 5-level design has been successfully implemented on a Xilinx Spartan 3E FPGA, utilising only 1104 slices for a 512-by-512 pixel test image, the lowest hardware requirements for a 5-level discrete wavelet transform processor reported to date.     

基于压缩感知的低功耗高效率CMOS图像传感器设计

提出一种基于压缩感知的低功耗高效率CMOS图像传感器(CIS)设计.在这种压缩感知CIS中,帧存储、帧差求解和帧压缩等过程分别集成于像素级、列级和芯片级电路中,实现了图像传感过程和图像压缩过程的融合.这种融合提高了CIS在功耗、传输带宽和输出数据等方面的效率.所提出的CIS设计已采用Global Foundries 0...     

基于神经网络的多光谱遥感图像无损压缩

分析并改进了利用自组织特征映射(SOFM)神经网络设计码书的方法,提出了一种基于改进SOFM算法设计码书的矢量量化和分类谱间预测相结合的多光谱图像无损压缩方法。该方法对光谱信息进行矢量量化,根据分类信息生成残差图像以去除数据的空间相关性,构造分类谱间预测器去除数据的谱间结构和统计相关性。对机载64波段多光谱遥感图像的试验结果表明,该方法无论是对训练集内图像还是训练集外图像,均取得了较好的压缩效果,平均无损压缩比达到3.2以上。     

Effective layer-based segmentation of compound images using morphology

Effective compound image compression algorithms require compound images to be first segmented into regions such as text, pictures and background to minimize the loss of visual quality of text during compression. In this paper, a new compound image segmentation algorithm based on the Mixed Raster Content model (MRC) of multilayer approach is proposed (foreground/mask/background). This algorithm first segments a compound image into different classes. Then each class is transformed to the three-layer MRC model differently according to the property of that class. Finally, the foreground and the background layers are compressed using JPEG 2000. The mask layer is compressed using JBIG2. The proposed morphological-based segmentation algorithm design a binary segmentation mask which partitions a compound image into different layers, such as the background layer and the foreground layer accurately. Experimental results show that it is more robust with respect to the font size, style, colour, orientation, and alignment of text in an uneven background. At similar bit rates, our MRC compression with the morphology-based segmentation achieves a much higher subjective quality and coding efficiency than the state-of-the-art compression algorithms, such as JPEG, JPEG 2000 and H.264/AVC-I.     

基于平铺数据流的可配置神经网络加速器

卷积神经网络已经是公认最好的用于深度学习的算法,被广泛地应用于图像识别、自动翻译和广告推荐。由于神经网络结构规模的逐渐增大,使其具有大量的神经元和突触,所以,使用专用加速硬件挖掘神经网络的并行性已经成为了热门的选择。在硬件设计中,经典的平铺结构实现了很高的性能,但是平铺结构的单元利用率很低。目前,随着众多深度学习应用对硬件性能要求的逐渐提高,加速器对单元利用率也具有越来越严格的要求。为了在平铺数据流结构上获得更高的单元利用率,可以调换并行的顺序,采用并行输入特征图和输出通道的方式来提高计算的并行性。但是,随着神经网络运算对硬件性能要求的提高,运算单元阵列必然会越来越大。当阵列大小增加到一定程度,相对单一的并行方式会使利用率逐渐下降。这就需要硬件可以开发更多的神经网络并行度,从而抑制单元空转。同时,为了适应不同的网络结构,要求硬件阵列对神经网络的运算是可配置的。但是,可配置硬件会极大地增加硬件开销和数据的调度难度。提出了一种基于平铺结构加速器的并行度可配置的神经网络加速器。为了减少硬件复杂度,提出了部分配置的技术,既能满足大型单元阵列下单元利用率的提升,也能尽可能地减少硬件额外开销。在阵列大小超过512之后,硬件单元利用率平均可以维持在82%～90%。同时加速器性能与单元阵列数量基本成线性比例上升。