微尺寸SnAg凸点的制备技术及其互连可靠性

用电镀法制备了尺寸小于100μm的面阵列Sn-3.0Ag凸点.芯片内凸点的高度一致性约1.42%,Φ100mm硅圆片内的高度一致性约3.57%,Ag元素在凸点中分布均匀.研究了不同回流次数下SnAg/Cu的界面反应和孔洞形成机理,及其对凸点连接可靠性的影响.回流过程中SnAg与Cu之间Cu6Sn5相的生长与奥氏熟化过程相似.SnAg/Cu6Sn5界面中孔洞形成的主要原因是相转变过程中发生的体积缩减.凸点的剪切强度随着回流次数的增多而增大,且多次回流后SnAg/Cu界面仍然结合牢固.Cu6Sn5/Cu平直界面中形成的孔洞对凸点的长期可靠性构成威胁.     

微尺寸SnAg凸点的制备技术及其互连可靠性

用电镀法制备了尺寸小于100μm的面阵列Sn-3.0Ag凸点.芯片内凸点的高度一致性约1.42%,Φ100mm硅圆片内的高度一致性约3.57%,Ag元素在凸点中分布均匀.研究了不同回流次数下SnAg/Cu的界面反应和孔洞形成机理,及其对凸点连接可靠性的影响.回流过程中SnAg与Cu之间Cu6Sn5相的生长与奥氏熟化过程相似.SnAg/Cu6Sn5界面中孔洞形成的主要原因是相转变过程中发生的体积缩减.凸点的剪切强度随着回流次数的增多而增大,且多次回流后SnAg/Cu界面仍然结合牢固.Cu6Sn5/Cu平直界面中形成的孔洞对凸点的长期可靠性构成威胁.     

焊料凸点回流时的桥接现象研究

在用回流焊料凸点时,常会发生凸点的桥接现象,致使芯片报废。此时,相邻的多个凸点彼此融合,聚集成一个更大的焊料球,并吸干先前各凸点中的焊料。本文研究了电镀PbSn凸点和蒸发铟凸点的回流过程中出现的桥接现象。介绍了桥接现象产生的过程及其背景,分析了桥接现象的机理,提出了改进措施。     

感应自加热重熔无铅焊料凸台的剪切失效模式

通过两次高频感应重熔制备了Cu焊盘上S n3．5Ag焊料和Sn3．0Ag0．5Cu焊料凸台,并进行了120℃下的老化试验以及老化试件的剪切强度试验,分析了不同老化时间下两种无铅焊料凸台的剪切断裂模式。焊料凸台的剪切载荷-位移曲线的特征以及对焊料凸台剪切断口的扫描电镜形貌分析结果表明,不同老化时间下无铅焊料凸台的剪切断裂表现为塑性、韧性和脆性三种断裂模式。对凸台焊料合金的组织以及界面观察结果表明,随老化时间不断生长的脆性金属间化合物层以及焊料组织粗大是致使断裂失效模式转变的根本原因。     

对Cu焊区的倒装芯片凸点下金属化系统的研究

本文研究了采用化学镀铜（E-Cu）和化学镀镍（E-Ni)方法制作的Cu焊区上倒装芯片焊料凸点用的UBM材料系统，还研究了UBM与Sn-36Pb-2Ag焊料之间的界面反应对焊料凸点连接可靠性的影响，以优化Cu焊区上倒装芯片用的UBM材料。对于E-CuUBM来说，在焊料/E-Cu界面上形成贝壳状的Cu6Sn5金属互化物（IMC），在较小的载荷下沿这个界面发生凸点断裂。与此相反，在E-Nie-Cu UBM的情况下，E-Ni成为一个好的扩散阻挡层。E-Ni有效地限制了IMC在该界面上的生长，而多边形形状的Ni3Sn4IMC产生比E-CuUBM高的附着强度。因此，化学镀沉积的UBM系统被成功地证明可作为低成本的Cu焊区上UBM方法。发现E-NiE-CuUBM材料是比E-Cu UBM更好的Cu焊区上倒装芯片焊料互连的材料。     

化学镀镍、模版印刷法制备倒扣芯片焊料凸点

回顾了低成本制备芯片上焊料凸点的方法,即化学镀镍制备凸点下金属层、模版印刷焊料,最后回流形成焊料凸点,并综述了该方法的最新研究进展.     

共晶Sn3.8Ag0.7Cu焊料在Fe-Ni镀层上的反应润湿行为

用电镀工艺制备了Fe-Ni镀层,研究了还原气氛保护下共晶Sn3.8Ag0.7Cu焊料在Fe-Ni镀层上的反应润湿行为。结果表明:在共晶Sn3.8Ag0.7Cu与Fe-74Ni反应润湿体系观察到了伪部分润湿行为。在铺展球冠的前沿,可以明显地看到有液态膜伸出主液体铺展前沿。随着回流时间的增加,液态膜逐渐长大。共晶Sn3.8Ag0.7Cu焊料与Fe-74Ni电镀合金层的液固界面生成了一层FeSn2化合物,还有大量Cu/Ni/Sn化合物进入焊料内部。     

用于3D集成的精细节距Cu/Sn微凸点倒装芯片互连工艺研究

芯片异构集成的节距不断缩小至10 μm及以下,焊料外扩、桥联成为焊料微凸点互连工艺的主要技术问题.通过对微凸点节距为8 μm的Cu/Sn固液扩散键合的工艺研究,探索精细节距焊料微凸点互连工艺存在的问题,分析Cu/Sn微凸点键合界面金属间的化合物,实现了精细节距和高质量的Cu/Sn微凸点互连,获得了节距为8 μm、微凸点...     

微量Co对低银无铅焊料润湿及界面反应的影响

利用润湿测量仪研究了加入微量Co对低银无铅焊料Sn1.00Ag0.70Cu和Sn0.50Ag0.70Cu润湿性能的影响,并与共晶无铅焊料Sn3.00Ag0.50Cu的润湿性能进行对比。结果发现,焊料Sn3.00Ag0.50Cu、Sn1.00Ag0.70Cu0.07Co和Sn0.50Ag0.70Cu0.03Co的润湿平衡力F分别为3.0850,3.0600和3.0275mN,润湿时间分别为0.64,0.88和1.01s。低银微钴无铅焊料显示了与共晶无铅焊料类似的润湿力,只是润湿时间略有增加。     

覆Ag层对用于LD封装的In焊料性能的影响

In焊料由于其优越的可塑性以及优良的导电、导热特性,被广泛用于半导体激光器(LD)的封装。但是In焊料遇空气易氧化,尤其在焊接加热的过程中,氧化现象更加明显,因此一般当天制备当天使用。为防止氧化,可以在In焊料表面镀一层Ag或Au作为保护层,因为Ag成本较Au低,可作为首选的保护层。关于In-Ag合金性能的研究已有过相关报道,但关于In-Ag合金的表面形貌及Ag层厚度对内部In的影响的报道还很少。文章通过扫描电子显微镜、XRD对不同样品进行了表面和成分的分析,得到了关于Ag对内部焊料的影响以及不同冷却速率下焊料的表面形貌。     

Preparation of Sn-Ag-In ternary solder bumps by electroplating in sequence and reliability

This paper describes a technique that can obtain ternary Sn-Ag-In solder bumps with fine pitch and homogenous composition distribution.The main feature of this process is that tin-silver and indium are electroplated on copper under bump metallization（UBM） in sequence.After an accurate reflow process,Sn_1.8Ag_9.4In solder bumps are obtained.It is found that the intermetallic compounds（IMCs） between Sn-Ag-In solder and Cu grow with the reflow time,which results in an increase in Ag concentration in the solder area.So during solidification, more Ag₂In nucleates and strengthens the solder.     

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 μm by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than ±0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260°C in N₂ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150°C for 1000 h in N₂ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs     

Under bump metallurgy study for Pb-free bumping

The demand for Pb-free and high-density interconnection technology is rapidly growing. The electroplating-bumping method is a good approach to meet finepitch requirements, especially for high-volume production, because to volume change of patterned-solder bumps during reflow is not so large compared with the stencil-printing method. This paper proposes a Sn/3.5 Ag Pb-free electroplating-bumping process for high-density Pb-free interconnects. It was found that a plated Sn/Ag bump becomes Sn/Ag/Cu by reflowing when Cu containing under bump metallurgy (UBM) is used. Another important issue for future flip-chip interconnects is to optimize the UBM system for high-density and Pb-free solder bumps. In this work, four UBM systems, sputtered TiW 0.2 μm/Cu 0.3 μm/electroplated Cu 5 μm, sputtered Cr 0.15 μm/Cr-Cu 0.3 μm/Cu 0.8 μm, sputtered NiV 0.2 μm/Cu 0.8 μm, and sputtered TiW 0.2 μm/NiV 0.8 μm, were investigated for interfacial reaction with electroplated Pb/63Sn and Sn/3.5Ag solder bumps. Both Cu-Sn and Ni-Sn intermetallic compound (IMC) growth were observed to spall-off from the UBM/solder interface when the solder-wettable layer is consumed during a liquid-state “reflow” process. This IMC-spalling mechanism differed depending on the barrier layer material.     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

Effects of Cu contents in Pb-free solder alloys on interfacial reactions and bump reliability of Pb-free solder bumps on electroless Ni-P under-bump metallurgy

Using the screen-printed solder-bumping technique on the electroless plated Ni-P under-bump metallurgy (UBM) is potentially a good method because of cost effectiveness. As SnAgCu Pb-free solders become popular, demands for understanding of interfacial reactions between electroless Ni-P UBMs and Cu-containing Pb-free solder bumps are increasing. It was found that typical Ni-Sn reactions between the electroless Ni-P UBM and Sn-based solders were substantially changed by adding small amounts of Cu in Sn-based Pb-free solder alloys. In Cu-containing solder bumps, the (Cu,Ni)₆Sn₅ phase formed during initial reflow, followed by (Ni,Cu)₃Sn₄ phase formation during further reflow and aging. The Sn3.5Ag solder bumps showed a much faster electroless Ni-P UBM consumption rate than Cu-containing solder bumps: Sn4.0Ag0.5Cu and Sn0.7Cu. The initial formation of the (Cu,Ni)₆Sn₅ phase in SnAgCu and SnCu solders significantly reduced the consumption of the Ni-P UBM. The more Cu-containing solder showed slower consumption rate of the Ni-P UBM than the less Cu-containing solder below 300°C heat treatments. The growth rate of the (Cu,Ni)₆Sn₅ intermetallic compound (IMC) should be determined by substitution of Ni atoms into the Cu sublattice in the solid (Cu,Ni)₆Sn₅ IMC. The Cu contents in solder alloys only affected the total amount of the (Cu,Ni)₆Sn₅ IMC. More Cu-containing solders were recommended to reduce consumption of the Ni-based UBM. In addition, bump shear strength and failure analysis were performed using bump shear test.     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Effects on Undercooling and Interfacial Reactions with Cu Substrates of Adding Bi and In to Sn-3Ag Solder

This study investigated the effects of adding Bi and In to Sn-3Ag Pb-free solder on undercooling, interfacial reactions with Cu substrates, and the growth kinetics of intermetallic compounds (IMCs). The amount of Sn dominates the undercooling, regardless of the amount or species of further additives. The interfacial IMC that formed in Sn-Ag-Bi-In and Sn-In-Bi solders is Cu₆Sn₅, while that in Sn-Ag-In solders is Cu₆(Sn,In)₅, since Bi enhances the solubility of In in Sn matrices. The activation energy for the growth of IMCs in Sn-Ag-Bi-In is nearly double that in Sn-Ag-In solders, because Bi in the solder promotes Cu dissolution. The bright particles that form inside the Sn-Ag-In bulk solders are the ζ-phase.     

Fabrication on uniform plating-based flip chip solder bumps after reflow process using a polishing mechanism

This paper presents an innovative polishing process aimed at leveling rough surface of plating-based flip chip solder bumps so as to get uniform coplanarity across the whole substrate after both electroplating and reflow processes. This polishing mechanism is characteristic of combining mechanical-dominated polishing force with slight chemical reaction together. A large number of extremely but inevitably rugged mushroom-like structures after electroplating are drastically smoothed down with the help of this newly-developed polishing process. Nearly 70 μm solder bumps in height with two different profiles as square and circle on the substrates reach as flatly as ±3 μm between different substrates after reflow process; ±2.5 μm in single substrate; and even ±1 μm in die, respectively. Besides, surface roughness among the solder bumps is simultaneously narrowed down from Ra 0.6 to Ra 0.03 along with the coplanarity improvement. Excellent uniformity and smooth surface roughness in solder bumps are absolutely beneficial to pile up and deposit in the following steps in MEMS and semiconductor fields.