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1.
Transient oxide-charge trapping and detrapping, commonly regarded as a parasitic effect in the interpretation of dynamic bias-temperature stress (BTS) data, may play an important role on the long term reliability of the gate oxide as revealed by recent studies on the SiON and HfO2 gate dielectrics. Specifically, it is found that transient charge trapping (one which relaxes upon removal of the applied electrical stress) is transformed into more permanent trapped charge when the applied electrical cum thermal stress exceeds a certain threshold. Below the threshold, cyclical transient charge trapping and detrapping behavior is observed. The observations imply that the oxide structure may be modified by the applied stress, making it susceptible to permanent defect generation. In addition, it is found that when the transformation of hole trapping occurs under negative-bias temperature stress, a correlated increase of the gate current is always observed, which points to the transformation process being the origin for bulk oxide trap generation. However, when the transformation of electron trapping occurs under positive-bias temperature stress, an increase of the gate current is not always observed. From ab initio simulation, we show that an intrinsic oxide defect – the oxygen vacancy-interstitial (VO − Oi) – could consistently explain the experimental observations. An interesting feature of the VO − Oi defect is that it can exists in various metastable configurations with the interstitial oxygen Oi in different positions around the vacancy VO, corresponding to different trap energy states in the oxide bandgap. This characteristic is able to account for the BTS induced generation of deep-level trapped charges as well as transformation of transient (or shallow) to permanent (or deep) charge trapping. 相似文献
2.
This work demonstrates that for constant oxide reliability stresses in the Fowler-Nordheim regime a low initial rate of charge trapping/detrapping results in long times to breakdown. It was found for MOS gate oxides that when the initial trapping has been completed at low fields times to breakdown enhance. Depending on the stress sequence measurement results can vary significantly which is of great relevance for correct oxide lifetime predictions. 相似文献
3.
本文详细地研究了关键尺寸的继续微缩对三维圆柱形无结型电荷俘获存储器器件性能的影响。通过Sentaurus三维器件仿真器,我们对器件性能的主要评价指标进行了系统地研究,包括编程擦除速度和高温下的纵向电荷损失及横向电荷扩散。沟道半径的继续微缩有利于操作速度的提升,但使得纵向电荷损失, 尤其是通过阻挡层的纵向电荷损失,变得越来越严重。栅极长度的继续微缩在降低操作速度的同时将导致俘获电荷有更为严重的横向扩散。栅间长度的继续微缩对于邻近器件之间的相互干扰有决定性作用,对于特定的工作温度及条件其值需谨慎优化。此外,栅堆栈的形状也是影响电荷横向扩散特性的重要因素。研究结果为高密度及高可靠性三维集成优化提供了指导作用。 相似文献
4.
Nikolaos Nikolaou Panagiotis Dimitrakis Pascal Normand Vassilios Ioannou-Sougleridis Konstantinos Giannakopoulos Konstantina Mergia Kaupo Kukli Jaakko Niinistö Mikko Ritala Markku Leskelä 《Solid-state electronics》2012
In this work we report the performance of the SiO2/Si3N4/HfO2 and SiO2/Si3N4/ZrO2 stacks with emphasis on the influence of atomic layer deposition chemistry used for forming the HfO2 and ZrO2 blocking layers. Two Hf precursors were employed – tetrakis(ethylmethylamino)hafnium (TEMAH) and bis(methylcyclopentadienyl)methoxymethyl hafnium (HfD-04). For ZrO2, tetrakis(ethylmethylamino)zirconium (TEMAZ) and bis(methylcyclopentadienyl)methoxymethyl zirconium (ZrD-04) were used as metal precursors. Ozone was used as the oxygen source. The structural characteristics of the stacks were examined by transmission electron microscopy and grazing incidence X-ray diffraction. The electrical properties of the stacks were studied using platinum-gated capacitor structures. The memory performance of the stacks was evaluated by write/erase (W/E) measurements, endurance and retention testing. Endurance measurements revealed the most important difference between the stacks. The films grown from TEMAH and TEMAZ could withstand a significantly higher number of W/E pulses (>3 × 105 in the 10 V/?11 V, 10 ms regime), in comparison to the stacks made from HfD-04 and ZrD-04 precursors (<5 × 103 W/E cycles). This difference in endurance characteristics is attributed mainly to the different deposition temperatures suited for these two precursors and the nature of the layer formed at the Si3N4/HfO2 and the Si3N4/ZrO2 interfaces. 相似文献
5.
Characterization of gate oxides grown on zone-melting-recrystallized (ZMR) and silicon-implanted-with-oxygen (SIMOX) films indicates oxide leakage and charge trapping to be several orders of magnitude greater than their bulk silicon counterparts. Electron trapping is the primary trapping mechanism for constant current injection in the gate oxides of these SOI (silicon-on-insulator) films. Similar type of traps are observed in ZMR and SIMOX oxides 相似文献
6.
Chen T.P. Jiayi Huang Tse M.S. Tan S.S. Ang C.H. 《Electron Devices, IEEE Transactions on》2003,50(6):1548-1550
This brief reports a study of charge injection-induced edge charge trapping in the gate oxide overlapping the drain extension which has an impact on the drain leakage current. The edge charge trapping is determined for the gate oxide thickness of 6.5, 3.9, and 2.0 nm by using a simple approach to analyze the change of the band-to-band tunneling current measured with a three-terminal gate-controlled-diode configuration. The edge charge trapping has a strong dependence on the gate oxide thickness, and it is different from the charge trapping in the oxide over the channel. A plausible explanation for both the oxide thickness dependence of the edge charge trapping and the difference between the edge charge trapping and the charge trapping over the channel is presented. 相似文献
7.
The accumulation process of trapped charges in a TANOS cell during P/E cycling is investigated via numerical simulation.The recombination process between trapped charges is an important issue on the retention of charge trapping memory.Our results show that accumulated trapped holes during P/E cycling can have an influence on retention,and the recombination mechanism between trapped charges should be taken into account when evaluating the retention capability of TANOS. 相似文献
8.
9.
Chin-Lung Cheng Chien-Wei Liu Kuei-Shu Chang-Liao Ping-Hung Tsai Jin-Tsong Jeng Sung-Wei Huang Bau-Tong Dai 《Solid-state electronics》2008,52(10):1530-1535
The CoxNiyO hybrid metal oxide nanoparticles (HMONs) embedded in the HfOxNy high-k dielectric as charge trapping nodes of the nonvolatile memory devices have been formed via the chemical vapor deposition using the Co/Ni acetate calcined and reduced in the Ar/NH3 ambient. A charge trap density of 8.96 × 1011 cm?2 and a flatband voltage shift of 500 mV were estimated by the appearance of the hysteresis in the capacitance–voltage (C–V) measurements during the ±5 V sweep. Scanning electron microscopy image displays that the CoxNiyO HMONs with a diameter of ~10–20 nm and a surface density of ~1 × 1010 cm?2 were obtained. The mechanism related to the writing characteristics are mainly resulted from the holes trapping. Compared with those devices with the CoxNiyO HMONs formed by the dip-coated technique, memory devices with the CoxNiyO HMONs fabricated by the drop-coated technique show improved surface properties between the CoxNiyO HMONs and the HfON as well as electrical characteristics. 相似文献
10.
Wang T. Chang T.-E. Chiang L.-P. Wang C.-H. Zous N.-K. Huang C. 《Electron Devices, IEEE Transactions on》1998,45(7):1511-1517
We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 104 times more efficient in trap generation than the hot electron stress in terms of injected charge 相似文献
11.
Mazumder M.K. Teramoto A. Komori J. Sekine M. Kawazu S. Mashiko Y. 《Electron Devices, IEEE Transactions on》1999,46(6):1121-1126
Wet pyrogenic oxide of different thicknesses was annealed in N2O ambient and the N concentration in the films was studied by using SIMS (secondary ion mass spectroscopy). It was found that for a certain annealing time and temperature, the N concentration (at %) increases with decreasing wet oxide thickness and the location of the peak of N is observed near the interface of nitrided oxide and Si substrate. On the contrary, after nitridation the concentration of H is higher in the thicker wet oxide of thickness 100 Å and also does not change much from the surface to the interface. For the thinner wet oxide of thickness 40 Å, the concentration of H is less and decreases toward the interface. Gate dielectrics were characterized using high-frequency and quasi-static measurements. After a constant current stress, a large distortion was observed for the N2O annealed wet oxide of 98 Å whereas for the N2O annealed wet oxide of 51 Å the distortion was small. With increasing stressing time, hole trap is followed by electron trapping for the wet oxide of 98 Å whereas for the N2O annealed wet oxide of 51 Å, hole trapping increases a little at the beginning and then saturates. From the TDDB characteristics, a longer tBD was observed for N2O annealed wet oxide of 51 Å compared to 98 Å. From the experimental results, it can be suggested that the improved reliability of thin gate oxide is due to the large amount of N concentration near the interface only. Hence for the device fabrication process, if the wet oxide is nitrided in N2O ambient, the reliability of gate oxide will be improved in the ultrathin region 相似文献
12.
The authors report the observation of trapping and aging effects in charge injection schemes for floating-gate devices. The observations indicate that these polysilicon charge injectors must be used in conjunction with a programming technique which includes feedback. A suitable scheme is chip-in-the-loop training 相似文献
13.
The effects of the titanium salicide (self-aligned silicide) process on the reliability of very-thin-gate-oxide MOSFETs have been studied. It is shown that the titanium salicide process, as compared to the conventional poly-Si gate process, has reduced electron and hole trapping in the oxide and improved hot-electron reliability. It is shown that these phenomena are related to the reduced hydrogen content in the oxide as revealed by a secondary ion mass spectrometry (SIMS) analysis 相似文献
14.
《Electron Devices, IEEE Transactions on》1979,26(4):421-429
Based on appropriate down scaling of devices and reasonable extrapolation of present technological possibilities, circuit performance of several LSI technologies has been calculated. From a set of impurity distributions, oxide thickness, etc., process parameters have been derived, which have been converted into transistor-model parameters for use in a circuit simulation program. Although for every technology a substantial improvement in performance is predicted, MOS appears to benefit most from scaling down. The speed of ED-MOS eventually rivals that of ECL and the speed-power product that of I2L. Below 1 µm gate width a delay time of 100 ps and a speed-power product of 20 fJ are possible. I2L is by far the slowest technology, but it has the best packing density. Current densities in MOS approach that of ECL. 相似文献
15.
Specht M. Kommling R. Hofmann F. Klandzievski V. Dreeskornfeld L. Weber W. Kretz J. Landgraf E. Schulz T. Hartwich J. Rosner W. Stadele M. Luyken R.J. Reisinger H. Graham A. Hartmann E. Risch L. 《Electron Device Letters, IEEE》2004,25(12):810-812
Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first time. Compared to a planar cell, the proposed tri-gate device architecture offers higher readout currents and improved electrostatic gate control of the channel region yielding very good scalability of the devices. We have investigated devices with gate lengths in the range L/sub G/=100-220 nm and we focus on their write-erase, retention, and cycling characteristics. 相似文献
16.
Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deep-submicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25-μm CMOS appears to be the threshold for robust, low-NF RF front ends with current consumption competitive with today's BJT implementations 相似文献
17.
Jan Felix Binder Peter BroqvistAlfredo Pasquarello 《Microelectronic Engineering》2011,88(7):1428-1431
Electron and hole trapping in substoichiometric germanium oxides are investigated through the use of hybrid density functionals. We consider disordered model structures generated by Monte-Carlo bond switching and by ab initio molecular dynamics (MD). The Monte-Carlo model consists of fourfold coordinated Ge atoms and of twofold coordinated O atoms, and does not show trap levels neither for electron nor for holes. At variance, the MD model shows threefold coordinated O and Ge atoms forming valence alternation pairs and is found to present trap states for both carriers. The trapping states correspond to the formation and breaking of Ge-Ge bonds. The associated defect levels are determined within a band diagram of the Ge/GeO2 interface. 相似文献
18.
To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density.The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis. 相似文献
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20.
The charge trapping properties of ultrathin HfO/sub 2/ in MOS capacitors during constant voltage stress have been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode are presented in this letter. It is shown that the generation of interface-trap density under constant-voltage stress is much more significant for samples with Pt gate electrodes than that with Al gates. The trapping-induced flatband shift in HfO/sub 2/ with Al gates increases monotonically with injection fluence for p-type Si substrates, while it shows a turnaround phenomenon for n-type Si substrates due to the shift of the charge centroid. The trapping-induced flatband shift is nearly independent of stress voltage for p-type substrates, while it increases dramatically with stress voltage for n-type Si substrates due to two competing mechanisms. The trap density can be reduced by increasing the annealing temperature from 500/spl deg/C to 600/spl deg/C. The typical trapping probability for JVD HfO/sub 2/ is similar to that for ALD HfO/sub 2/. 相似文献