Statistical RTS model for digital circuits

In this work we study the variation in drain current of MOS transistors due to the capture and emission of electrons at interface states (traps), called random telegraph signal (RTS). Usually, RTS is studied in frequency domain. However, for digital circuits, it is more appropriate to use time-domain representations.The time-domain representation here proposed models the effect of RTS on I_ds as instantaneous Vt shifts. We introduce a statistical numerical approach for computing the total ΔVt of the transistor considering all the traps in the interface. The method analyses the effect of non-uniform charge densities along the channel. To show the applicability of the methodology to circuit analysis on the electrical level, the model is applied to characterize read and write instability failures caused by RTS on a 6T-SRAM cell.     

Characterization of oxide traps in 0.15 μm MOSFETs using random telegraph signals

Random telegraph signals (RTS) have been used to characterize oxide traps of W×L=0.97×0.15 μm² medium-doped drain n-MOSFETs. RTS have been measured in the linear and saturation regions of operation, both in forward and reverse modes where the drain and source are reversed. The contribution of mobility fluctuations as well as number fluctuations to the amplitude of RTS has been investigated. The scattering coefficient due to screened Coulomb scattering effect is computed from the measured data as a function of channel carrier density. The depth of the position of the trap in the oxide from Si–SiO₂ interface is calculated utilizing the dependence of the emission and capture times on the gate voltage. In addition, the position of the trap along the channel with respect to the source is obtained using the difference in the drain voltage dependence of the capture and emission times between the forward and reverse modes. Knowing the location of the trap in the oxide and along the channel, the energy associated with the trap can be extracted accurately from the data. This technique allows one to evaluate the trap energy at the point where the trap is located without any assumptions about the location of the trap or the need for variable temperature measurements. The probed trap was found to be an acceptor type center (repulsive for an n-MOSFET) located at about 27 Å deep the oxide, half-way between drain and source with an energy of E_Cox−E_T=3.04 eV, slightly above the conduction band edge.     

A method for locating the position of oxide traps responsible forrandom telegraph signals in submicron MOSFETs

Random telegraph signals (RTS) have been measured in the drain to source voltage of W×L=0.97×0.15 μm² medium-doped drain (MDD) n-MOSFET's. The depth of the trapping center in the oxide is found from the gate voltage dependence of the emission and capture times. The difference in the drain voltage dependence of the capture and emission times between the forward and reverse modes is utilized to find the position of the trap in the channel with respect to the source     

The impact of static and dynamic degradation on SOI “smart-cut” floating body MOSFETs

The impact of static (DC) and dynamic (AC) degradation on SOI “smart-cut” floating body MOSFETs, was investigated by means of deep level transient spectroscopy (DLTS). The study was based on drain current signal recording, immediately after the transistor transition from OFF- to ON-state. In order to isolate the activity of capture/emission carrier mechanisms, undesirable parasitic effects such as drain current overshoot were suppressed by appropriately biasing the transistor substrates. Under DC degradation regime, DLTS spectra disclosed that carrier capture/emission process occurred through discrete traps governed by thermally activated mechanisms. Furthermore, polarization phenomena emerged. Under AC degradation regime, although the existence of interface states in Si-SiO2 interface was dominant, the revelation of shallow traps in low temperature domain was also monitored.     

Traps centers and deep defects contribution in current instabilities for AlGaN/GaN HEMT's on silicon and sapphire substrates

AlGaN/GaN high electron mobility transistors (HEMTs) with Si and Al₂O₃ substrates reveals anomalies on I_ds-V_ds-T and I_gs-V_gs-T characteristics (degradation in drain current, kink effect, barrier height fluctuations, etc.). Stress and random telegraph signal (RTS) measurements prove the presence of trap centers responsible for drain current degradation. An explanation of the trapping mechanism responsible for current instabilities is proposed. Deep defects analysis performed by capacitance transient spectroscopy (C-DLTS), frequency dispersion of the output conductance (G_ds(f)), respectively, on gate/source and drain/source contacts and RTS prove the presence of deep defects localized, respectively, in the gate and in the channel regions. Defects detected by C-DLTS and G_ds(f) are strongly correlated, respectively, to barrier height inhomogeneities and kink anomalies. Gate current analysis confirms the presence of (G-R) centers acting like traps at the interface GaN/AlGaN. Finally, the localization of these traps defects is proposed.     

Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs

Random telegraph signals (RTS) have been investigated in the drain to source voltage of W_eff×L_eff=1.37×0.17 μm² medium-doped drain (MDD) n-type MOSFETs. The emission (τ_e) and capture (τ_c) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τ_e and τ_c including the influence of bulk bias (V_SB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO₂ interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔV_DS/V_DS) shows a positive dependence on V_SB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.     

Impact of interface traps on gate-induced drain leakage current in n-type metal oxide semiconductor field effect transistor

As the features sizes of metal oxide semiconductor field effect transistor (MOSFET) are aggressively scaled into the submicron domain, hot carriers generated by the very large electric fields of drain region create serious reliability problems for the integrated circuit in MOS technology. The charges trapping in the gate oxide and the defects at the Si/SiO₂ interface have also undesirable effects on the degradation and ageing of MOSFET. Among the problems caused by these effects is the band-to-band tunnelling (BBT) of hot carriers in the gate-to-drain overlap region which is the source of the gate-induced drain leakage current I _gidl. The oxide charges shift the flat-band voltage and result in an enhancement of the I _gidl current. On the other hand, the generation of interface traps introduce an additional band-trap-band (BTB) leakage mechanism and lead to a significant increase ?I _gidl in a drain leakage current. In this work we propose a new method to calculate the I _gidl current which takes into account of the BTB leakage mechanism in order to clarify the impact of interface traps located in the gate-to-drain overlap region on the I _gidl current.     

Random telegraph signals in deep submicron n-MOSFET's

Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained both by number and mobility fluctuations due to single electron trapping in the gate oxide. The role of the type of the trap (acceptor or donor), the distance of the trap from the Si-SiO₂ interface, the channel electron concentration (which is set by the gate bias) and the electron mobility (which is affected by the drain voltage) is demonstrated. The effect of capture and emission on average electron mobility is demonstrated for the first time. A simple theoretical model explains the observed effect of electron heating on electron capture. The mean capture time depends on the local velocity and the nonequilibrium temperature of channel electrons near the trap. The difference between the forward and reverse modes (source and drain exchanged) provides an estimate of the effective trap location along the channel     

MOSFET中大幅度随机电报信号噪声的动力学特性

对 MOSFET器件的随机电报信号噪声 ( RTS)的特征进行了研究。室温下在极细沟道样品中观测到了大幅度 (大于 60 % )的 RTS,通过测量 RTS的俘获时间和发射时间与栅压和温度的依赖关系 ,获得了氧化层陷阱的位置与能级 ,证实了氧化层陷阱的热激活模型在细沟道 n MOSFET中仍然成立。同时发现当器件工作在弱反型区时 ,RTS幅度基本与栅压无关。对 RTS的动力学机制的分析及数值模拟表明 ,当沟道宽度减小至 4 0 nm以下时 ,由荷电陷阱对沟道载流子散射而产生的迁移率涨落对 RTS的幅度的影响起主导作用。     

A large-signal equivalent circuit model for substrate-induceddrain-lag phenomena in HJFETs

A large-signal HJFET model is developed for drain-lag phenomena caused by deep traps beneath the channel. The model is based on the self-backgating and Shockley-Read-Hall (SRH) statistics. It is shown by two-dimensional (2D) device simulation that electron capture in deep traps is much faster than electron emission under large-signal conditions; therefore, drain current exhibits different responses for rising and falling steps of applied voltage. In the circuit model, electron capture and emission in deep traps are expressed by a parallel circuit consisting of a diode and a resistor, which are physically deduced from SRH statistics. The model agrees well with the 2D simulation results and experimental current-transient data for large-signal voltage steps. In addition, this model accurately describes small-signal drain-conductance dispersion and temperature effects on the trapping phenomena     

Random telegraph signal: A sensitive and nondestructive tool for gate oxide single trap characterization

This paper presents the electrical characterization of thick and thin SiO₂ oxynitride performed by thermal and plasma nitridation processes. The impact of the nitridation technique is investigated using random telegraph signal (RTS) noise analysis. The variation of the gate oxide trap characteristics is determined with respect to the nitridation technique. Significant properties of traps are also pointed out. Main trap parameters, such as their depth with respect to the interface, nature, capture and emission times are extracted. These results illustrate the potential of RTS noise investigation for gate oxide characterizations.     

Traps centers impact on Silicon nanocrystal memories given by Random Telegraph Signal and low frequency noise

This work reports on a comprehensive process of trapping centers in Silicon nanocrystal (nc-Si) memories devices. The trap centers have been studied using Random Telegraph Signal (RTS) and Low Frequency (LF) techniques. The study of the traps which are responsible for RTS noise in non-volatile memories (NVM) devices as a function of gate voltage and temperature, offers the opportunity of studying the trapping/detrapping behaviour of a single interface trap center. The RTS parameters of the devices having random discrete fluctuations in the drain current get more information about trap energy level and spatial localization from the SiO₂/Si interface. The impact of trap centers has been also investigated showing the significant noise between memories and references devices. Furthermore, it has convincingly been shown that this discrete switching of the drain current between a high and a low state is the basic feature responsible for l/f^γ flicker noise in MOSFETs transistors.     

Defect localization induced by hot carrier injection in short-channel MOSFETs: Concept, modeling and characterization

Key aspects related to the localization of the hot-carrier induced damage in short channel MOSFET's are reviewed. Emphasis is put on the analysis, modeling and characterization of the degradation of device parameters caused by defects created locally beside the drain junction. Numerical simulations as well as analytical models predicting the post-stress performance are presented, compared and their limits of validity highlighted. Relevant experimental results, concerning the evolution of the static characteristics I_D(V_G, V_D) during transistor aging, are thoroughly discussed and efficient methods for the extraction of the defective region parameters are proposed. More specific techniques (charge pumping, noise spectroscopy, floating gate current, gated diode leakage), used for the characterization of aging induced defects, are evaluated from the point of view of their capability to cope with the localized nature of the defects. The merits of silicon on insulator structures and other technological solutions proposed for the attenuation of hot carrier effects are briefly commented.     

Correlation between dark current RTS noise and defects for AlGaInP multiple-quantum-well laser diode

推导了AlGaInP多量子阱LD器件暗电流RTS 噪声与缺陷相关性模型,实验结果表明暗电流RTS 噪声由有源区异质结界面载流子数涨落引起。根据相关性模型,确定了缺陷类型,定量确定了缺陷能级。分析了暗电流RTS 噪声功率谱密度的转角频率。实验结果和理论预测一致。本文结论提供一种确定AlGaInP多量子阱LD器件有源区深能级的有效方法。     

Low complexity hybrid layered tabu-likelihood ascent search for large MIMO detection with perfect and estimated channel state information

In this work, we proposed a low-complexity hybrid layered tabu-likelihood ascent search (LTLAS) algorithm for large multiple-input multiple-output (MIMO) system. The conventional layered tabu search (LTS) approach involves many partial reactive tabu searches (RTSs), and each RTS requires an initialization and searching phase. In the proposed algorithm, we restricted the upper limit of the number of RTS operations. Once RTS operations exceed the limit, RTS will be replaced by low-complexity likelihood ascent search (LAS) operations. The block-based detection approach is considered to maintain a higher signal-to-noise ratio (SNR) detection performance. An efficient precomputation technique is derived, which can suppress redundant computations. The simulation results show that the bit error rate (BER) performance of the proposed detection method is close to the conventional LTS method. The complexity analysis shows that the proposed method has significantly lower computational complexity than conventional methods. Also, the proposed method can reduce almost 50% of real operations to achieve a BER of 10⁻³.     

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

Study of passivation defects by electroluminescence in AlGaN/GaN HEMTS on SiC

This paper presents a new method of passivation control by electroluminescence (EL) in 0.15 μm AlGaN/GaN HEMT. The electroluminescence signature in one finger HEMTs (W = 1 × 100 μm), and eight fingers ones (W = 8 × 125 μm), is modified by defects located at the passivation/semiconductor interface and is characterized by a light emission along the drain contact. This abnormal emission reveals some modification of the electric field distribution in the gate-drain space probably induced by traps located at the passivation/semiconductor interface. These traps contribute to the creation of a virtual gate in the gate-drain space.     

Gate length effect on the RTS noise amplitude in SOI MOSFETs

The Random Telegraph Signal (RTS) noise amplitude in Silicon-on-Insulator MOSFETs is studied as a function of the gate length, by adding a second transistor in series. Different types of behavior can be distinguished, pointing toward a different origin of the related trapping centers. It is shown that in linear operation, the RTS amplitude and the corresponding low-frequency noise peak magnitude normally scales with 1/L. However, an increase with device length can also be found when the noise peaks of two RTSs add up. For RTSs occurring in the saturation regime, a complete elimination is observed for larger Ls, in support of the supposed film-related origin     

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current-voltage (I-V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I-V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco^®-TCAD). The proposed model also illustrates the effectiveness of the gate-source distance scaling effect compared to the gate-drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I-V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.     

Temperature and voltage dependences of the capture and emission times of individual traps in high-k dielectrics

Quantized threshold voltage (VTH) relaxation transients are observed in nano-scaled field effect transistors (FETs) after bias temperature stress. The abrupt steps are due to trapping/detrapping of individual defects in the gate oxide and indicate their characteristic emission/capture times. Individual traps are studied in n-channel SiO₂/HfSiO FETs after positive gate stress to complement previous studies performed on SiO(N). Similarly to single SiO(N) traps, strong thermal and bias dependences of the emission and capture times are demonstrated. The high-k traps have a higher density but a reduced impact on VTH due to their separation from the channel.